Datasheet

© 2008 Microchip Technology Inc. DS39768D-page 47
PIC24FJXXXGA0XX
6.2 Checksum Computation
Checksums for the PIC24FJXXXGA0XX family are
16 bits in size. The checksum is calculated by summing
the following:
• Contents of code memory locations
• Contents of Configuration registers
Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
byte at a time, using only their native data size. More
specifically, Configuration registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
TABLE 6-4: CHECKSUM COMPUTATION
Device
Read Code
Protection
Checksum Computation
Erased
Checksum
Value
Checksum with
0xAAAAAA at 0x0 and Last
Code Address
PIC24FJ16GA002
Disabled CFGB + SUM(0:02BFB) 0xBB5A 0xB95C
Enabled 0 0x0000 0x0000
PIC24FJ16GA004
Disabled CFGB + SUM(0:02BFB) 0xBB5A 0xB95C
Enabled 0 0x0000 0x0000
PIC24FJ32GA002
Disabled CFGB + SUM(0:057FB) 0x795A 0x775C
Enabled 0 0x0000 0x0000
PIC24FJ32GA004
Disabled CFGB + SUM(0:057FB) 0x795A 0x775C
Enabled 0 0x0000 0x0000
PIC24FJ48GA002
Disabled CFGB + SUM(0:083FB) 0x375A 0x355C
Enabled 0 0x0000 0x0000
PIC24FJ48GA004
Disabled CFGB + SUM(0:083FB) 0x375A 0x355C
Enabled 0 0x0000 0x0000
PIC24FJ64GA002
Disabled CFGB + SUM(0:0ABFB) 0xFB5A 0xF95C
Enabled 0 0x0000 0x0000
PIC24FJ64GA004
Disabled CFGB + SUM(0:0ABFB) 0xFB5A 0xF95C
Enabled 0 0x0000 0x0000
PIC24FJ64GA006
Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE
Enabled 0 0x0000 0x0000
PIC24FJ64GA008
Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE
Enabled 0 0x0000 0x0000
PIC24FJ64GA010
Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE
Enabled 0 0x0000 0x0000
PIC24FJ96GA006
Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE
Enabled 0 0x0000 0x0000
PIC24FJ96GA008
Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE
Enabled 0 0x0000 0x0000
PIC24FJ96GA010
Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE
Enabled 0 0x0000 0x0000
Legend: Item
Description
SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked),
64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3)
28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7)
Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2).