Datasheet
PIC24FJXXXGA0XX
DS39768D-page 4 © 2008 Microchip Technology Inc.
Pin Diagrams
PIC24FJXXGA002
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin PDIP, SSOP, SOIC
28-Pin QFN
(1)
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
PIC24FJXXGA002
5
4
MCLR
VSS
VDD
RA0
RA1
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
RA4
RB4
RA3
RA2
RB3
RB2
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5
V
DD
VSS
PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6
DISVREG
V
CAP/VDDCORE
RB7
RB9
RB8
RB15
RB14
RB13
RB12
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
V
SS
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0
RA3
RA2
RB3
RB2
PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
DISVREG
V
CAP/VDDCORE
RB9
RB13
RB12
PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10
PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11
VDD
PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6
RA4
RB4
RB7
RB8
PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5
MCLR
RA0
RA1
V
DD
Vss
RB15
RB14
Legend: RPx represents remappable peripheral pins.
Note 1: The bottom pad of QFN packages should be connected to V
SS.