PIC24FJXXXGA0XX PIC24FJXXXGA0XX Flash Programming Specification 1.0 DEVICE OVERVIEW This document defines the programming specification for the PIC24FJXXXGA0XX family of 16-bit microcontroller devices. This programming specification is required only for those developing programming support for the PIC24FJXXXGA0XX family. Customers using only one of these devices should use development tools that already provide support for device programming.
PIC24FJXXXGA0XX The regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as tantalum) must be connected to the VDDCORE pin (Figure 2-2 and Figure 2-3). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section 7.0 “AC/DC Characteristics and Timing Requirements”. FIGURE 2-3: CONNECTIONS FOR THE ON-CHIP REGULATOR (28/44-PIN DEVICES) Regulator Enabled (DISVREG tied to VSS): 3.
PIC24FJXXXGA0XX 2.2 Program Memory Write/Erase Requirements 2.3 The pin diagrams for the PIC24FJXXXGA0XX family are shown in the following figures. The pins that are required for programming are listed in Table 2-1 and are shown in bold letters in the figures. Refer to the appropriate device data sheet for complete pin descriptions. The Flash program memory on the PIC24FJXXXGA0XX devices has a specific write/erase requirement that must be adhered to for proper device operation.
PIC24FJXXXGA0XX Pin Diagrams MCLR RA0 RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FJXXGA002 28-Pin PDIP, SSOP, SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS RB15 RB14 RB13 RB12 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG RB9 RB8 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 RA1 RA0 MCLR VDD Vss RB15 RB14 28-Pin QFN(1) 28 27
PIC24FJXXXGA0XX Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin QFN(1) PIC24FJXXGA004 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA7 RB14 RB15 AVSS AVDD MCLR RA0 RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/R
PIC24FJXXXGA0XX Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin TQFP PIC24FJXXGA004 33 32 31 30 29 28 27 26 25 24 23 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RA10 RA7 RB14 RB15 AVSS AVDD MCLR RA0 RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP1
PIC24FJXXXGA0XX Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE4 RE3 RE2 RE1 RE0 RF1 RF0 ENVREG VCAP/VDDCORE RD7 RD6 RD5 RD4 RD3 RD2 RD1 64-Pin TQFP RE5 RE6 RE7 RG6 RG7 RG8 MCLR RG9 VSS VDD RB5 RB4 RB3 RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24FJXXGA006 PIC24FJXXXGA006 48 RC14 47 46 45 44 43 42 41 40 RC13 39 38 37 RC12 VDD RG2 36 35 34 33 RG3 RF6 RD0 RD11 RD10 RD9 RD8 Vss RC15 RF2 RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVD
PIC24FJXXXGA0XX Pin Diagrams (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RE4 RE3 RE2 RE1 RE0 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE RD7 RD6 RD5 RD4 RD13 RD12 RD3 RD2 RD1 80-Pin TQFP RE5 RE6 RE7 RC1 RC3 RG6 RG7 RG8 MCLR RG9 VSS VDD RE8 RE9 RB5 RB4 RB3 RB2 PGC1/EMUC1/AN1/CN3/RB1 2 3 4 5 6 7 8 9 10 11 12 PIC24FJXXGA008 PIC24FJXXXGA008 13 14 15 16 17 18 19 20 RC14 RC13 RD0 RD11 RD10 RD9 RD8 RA15 RA14 VSS RC15 RC12 VDD RG2 RG3 RF6 RF7 RF8 RF2 RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMU
PIC24FJXXXGA0XX Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RE4 RE3 RE2 RG13 RG12 RG14 RE1 RE0 RA7 RA6 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE RD7 RD6 RD5 RD4 RD13 RD12 RD3 RD2 RD1 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC24FJXXGA010 PIC24FJXXXGA010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS RC14 RC13 RD0 RD11 RD10 RD9 RD8 RF2 RA14 VSS RC15 RC12 VDD TDO TDI RA3 RA2 RG2 RG3
PIC24FJXXXGA0XX 2.4 Memory Map The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map and supports up to 44K instruction words (about 128 Kbytes). Table 2-3 shows the program memory size and number of erase and program blocks present in each device variant. Each erase block, or page, contains 512 instructions, and each program block, or row, contains 64 instructions. Locations 800000h through 8007FEh are reserved for executive code memory.
PIC24FJXXXGA0XX FIGURE 2-4: PROGRAM MEMORY MAP 000000h User Flash Code Memory (44031 x 24-bit) User Memory Space Configuration Words (2 x 24-bit) 0157FAh(1) 0157FCh(1) 0157FEh(1) 015800h(1) Reserved 7FFFFEh 800000h Executive Code Memory (1024 x 24-bit) Diagnostic and Calibration Words (8 x 24-bit) 8007EEh 8007F0h Configuration Memory Space 800800h Reserved Device ID (2 x 16-bit) Reserved Note 1: FEFFFEh FF0000h FF0002h FF0004h FFFFFEh The address boundaries for user Flash code memory are devi
PIC24FJXXXGA0XX 3.0 DEVICE PROGRAMMING – ICSP FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW ICSP mode is a special programming protocol that allows you to read and write to PIC24FJXXXGA0XX device family memory. The ICSP mode is the most direct method used to program the device; note, however, that Enhanced ICSP is faster. ICSP mode also has the ability to read the contents of executive memory to determine if the programming executive is present.
PIC24FJXXXGA0XX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up, resulting in a 9-bit SIX command instead of the normal 4-bit SIX command. The SIX control code allows execution of the PIC24FJXXXGA0XX family assembly instructions.
PIC24FJXXXGA0XX 3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION Note 1: After the contents of VISI are shifted out, the PIC24FJXXXGA0XX device maintains PGDx as an output until the first rising edge of the next clock is received. The REGOUT control code allows for data to be extracted from the device in ICSP mode. It is used to clock the contents of the VISI register, out of the device, over the PGDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles.
PIC24FJXXXGA0XX 3.3 Entering ICSP Mode The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. As shown in Figure 3-4, entering ICSP Program/Verify mode requires three steps: 1. 2. 3. MCLR is briefly driven high, then low.
PIC24FJXXXGA0XX 3.4 Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS Flash memory write and erase operations are controlled by the NVMCON register. Programming is performed by setting NVMCON to select the type of erase operation (Table 3-2) or write operation (Table 3-3) and initiating the programming by setting the WR control bit (NVMCON<15>). In ICSP mode, all programming operations are self-timed.
PIC24FJXXXGA0XX TABLE 3-4: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON to erase all program memory. 0000 0000 2404FA 883B0A MOV MOV #0x404F, W10 W10, NVMCON Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased.
PIC24FJXXXGA0XX 3.6 Writing Code Memory The procedure for writing code memory is the same as the procedure for writing the Configuration registers, except that 64 instruction words are programmed at a time. To facilitate this operation, working registers, W0:W5, are used as temporary holding registers for the data to be programmed.
PIC24FJXXXGA0XX TABLE 3-5: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Data (Hex) Description Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.
PIC24FJXXXGA0XX FIGURE 3-7: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at N=N+1 No All bytes written? Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Poll for WR bit to be Cleared No All locations done? Yes Done DS39768D-page 20 © 2008 Microchip Technology Inc.
PIC24FJXXXGA0XX 3.7 Writing Configuration Words The PIC24FJXXXGA0XX family configuration is stored in Flash Configuration Words at the end of the user space program memory and in multiple register Configuration Words located in the test space. These registers reflect values read at any Reset from program memory locations. The values can be changed only by programming the content of the corresponding Flash Configuration Word and resetting the device.
PIC24FJXXXGA0XX TABLE 3-7: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. 0000 2xxxx7 MOV , W7 Step 3: Set the NVMCON register to program CW2. 0000 0000 24003A 883B0A MOV MOV #0x4003, W10 W10, NVMCON Step 4: Initialize the TBLPAG register.
PIC24FJXXXGA0XX 3.8 Reading Code Memory Reading from code memory is performed by executing a series of TBLRD instructions and clocking out the data using the REGOUT command. Table 3-8 shows the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the 24-bit starting source address for reading is loaded into the TBLPAG register and W6 register.
PIC24FJXXXGA0XX 3.9 Reading Configuration Words The procedure for reading configuration memory is similar to the procedure for reading code memory, except that 16-bit data words are read (with the upper byte read being all ‘0’s) instead of 24-bit words. Since there are two Configuration registers, they are read one register at a time. TABLE 3-9: Command (Binary) Table 3-9 shows the ICSP programming details for reading the Configuration Words.
PIC24FJXXXGA0XX 3.10 Verify Code Memory and Configuration Word The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. The Configuration registers are verified with the rest of the code. The verify process is shown in the flowchart in Figure 3-8. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 3.
PIC24FJXXXGA0XX TABLE 3-10: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W0) for TBLRD instruction.
PIC24FJXXXGA0XX 4.0 DEVICE PROGRAMMING – ENHANCED ICSP This section discusses programming the device through Enhanced ICSP and the programming executive. The programming executive resides in executive memory (separate from code memory) and is executed when Enhanced ICSP Programming mode is entered. The programming executive provides the mechanism for the programmer (host device) to program and verify the PIC24FJXXXGA0XX devices using a simple command set and communication protocol.
PIC24FJXXXGA0XX FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE 4.3 Entering Enhanced ICSP Mode As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. 2. 3. Start Enter ICSP™ Mode The MCLR pin is briefly driven high, then low. A 32-bit key sequence is clocked into PGDx. MCLR is then driven high within a specified period of time and held. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FJXXXGA0XX devices.
PIC24FJXXXGA0XX 4.4 Blank Check FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY The term “Blank Check” implies verifying that the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as ‘1’. Start The Device ID registers (FF0002h:FF0000h) can be ignored by the Blank Check since this region stores device information that cannot be erased. The device Configuration registers are also ignored by the Blank Check.
PIC24FJXXXGA0XX 4.5.2 PROGRAMMING VERIFICATION After code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’s buffer. The READP command can be used to read back all of the programmed code memory. Alternatively, you can have the programmer perform the verification after the entire device is programmed using a checksum computation. 4.6 4.6.
PIC24FJXXXGA0XX TABLE 4-2: Bit Field (1) PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register Description ICS CW1<8> ICD Pin Placement Select bit 11 = ICD EMUC/EMUD pins are shared with PGC1/PGD1 10 = ICD EMUC/EMUD pins are shared with PGC2/PGD2 01 = ICD EMUC/EMUD pins are shared with PGC3/PGD3 00 = Reserved; do not use IESO CW2<15> Internal External Switchover bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled IOL1WAY(1) CW2<4> IOLOCK Bit One-Way Set Enable
PIC24FJXXXGA0XX 4.6.2 PROGRAMMING METHODOLOGY 4.6.4 CODE-PROTECT CONFIGURATION BITS Configuration bits may be programmed a single byte at a time using the PROGW command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented or reserved bits must be programmed with a ‘1’. CW1 Configuration register controls code protection for the PIC24FJXXXGA0XX family. Two forms of code protection are provided.
PIC24FJXXXGA0XX FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW Start ConfigAddress = 0157FCh(1) Send PROGW Command Is PROGW response PASS? No Yes ConfigAddress = ConfigAddress + 2 No Is ConfigAddress 0157FEh?(1) Yes Failure Report Error Finish Note 1: 4.7 Configuration Word addresses for PIC24FJ128GA devices are shown. Refer to Table 2-2 for others. Exiting Enhanced ICSP Mode Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 4-6.
PIC24FJXXXGA0XX 5.0 THE PROGRAMMING EXECUTIVE 5.1 Programming Executive Communication FIGURE 5-2: P1 1 The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. PGCx All communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the programming executive.
PIC24FJXXXGA0XX FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 Programming Executive Processes Command Host Clocks Out Response 1 15 16 2 15 16 1 2 15 16 PGCx PGDx MSB X X X LSB 1 P8 P20 The programming executive command set is shown in Table 5-1. This table contains the opcode, mnemonic, length, time-out and description for each command. Functional details on each command are provided in Section 5.2.4 “Command Descriptions”. 5.2.
PIC24FJXXXGA0XX TABLE 5-1: Opcode PROGRAMMING EXECUTIVE COMMAND SET Mnemonic Length (16-bit words) Time-out 1 ms Sanity check. Read an 8-bit word from the specified Device ID register. Description 0h SCHECK 1 1h READC 3 1 ms 2h READP 4 1 ms/row 3h RESERVED N/A N/A This command is reserved. It will return a NACK. 4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers. 5h PROGP 99 5 ms Program one row of code memory at the specified address, then verify.
PIC24FJXXXGA0XX 5.2.6 15 READC COMMAND 12 11 5.2.7 8 7 Opcode 0 15 12 11 8 7 Opcode Length N READP COMMAND 0 Length N Addr_MSB Reserved Addr_LS Addr_MSB Addr_LS Field Description Field Description Opcode 1h Length 3h Opcode 2h N Number of 8-bit Device ID registers to read (max. of 256) Length 4h N Number of 24-bit instructions to read (max.
PIC24FJXXXGA0XX 5.2.8 PROGC COMMAND 15 12 11 5.2.9 8 7 Opcode 0 15 12 11 8 7 Opcode Length Reserved PROGP COMMAND 0 Length Reserved Addr_MSB Addr_MSB Addr_LS Addr_LS Data D_1 D_2 Field Opcode ...
PIC24FJXXXGA0XX 5.2.10 PROGW COMMAND 15 12 11 5.2.11 8 7 Opcode 0 Length Data_MSB 15 QBLANK COMMAND 12 11 Opcode 0 Length Addr_MSB PSize_MSW Addr_LS PSize_LSW Data_LS Field Field Description Description Opcode Ah Dh Length 3h Length 4h PSize Reserved 0h Length of program memory to check in 24-bit words plus one (max.
PIC24FJXXXGA0XX 5.2.12 5.3.1 QVER COMMAND 15 12 11 0 Opcode Length Field Description Opcode Bh Length 1h All programming executive responses have a general format consisting of a two-word header and any required data for the command. 15 12 11 Opcode Expected Response (2 words): 1BMNh (where “MN” stands for version M.N) 0002h Programming Executive Responses The programming executive sends a response to the programmer for each command that it receives.
PIC24FJXXXGA0XX 5.3.1.3 QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all other commands. When the programming executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data. The format of the QE_Code for both queries is shown in Table 5-3.
PIC24FJXXXGA0XX 5.4 Programming the Programming Executive to Memory 5.4.1 OVERVIEW If it is determined that the programming executive is not present in executive memory (as described in Section 4.2 “Confirming the Presence of the Programming Executive”), it must be programmed into executive memory using ICSP, as described in Section 3.0 “Device Programming – ICSP”. TABLE 5-5: Command (Binary) Storing the programming executive to executive memory is similar to normal programming of code memory.
PIC24FJXXXGA0XX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 7: Repeat Steps 5 and 6 to erase the second page of executive memory. The W1 Pointer should be incremented by 400h to point to the second page. Step 8: Initialize TBLPAG and NVMCON to write stored diagnostic and calibration as single words. Initialize W1 and W2 as Write and Read Pointers to rewrite stored Diagnostic and Calibration Words.
PIC24FJXXXGA0XX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 15: Set the Read Pointer (W6) and load the (next four write) latches.
PIC24FJXXXGA0XX 5.4.2 PROGRAMMING VERIFICATION After the programming executive has been programmed to executive memory using ICSP, it must be verified. Verification is performed by reading out the contents of executive memory and comparing it with the image of the programming executive stored in the programmer. TABLE 5-6: Command (Binary) Reading the contents of executive memory can be performed using the same technique described in Section 3.8 “Reading Code Memory”.
PIC24FJXXXGA0XX 6.0 DEVICE DETAILS 6.1 Device ID TABLE 6-1: DEVICE IDs Device DEVID PIC24FJ16GA002 0444h The Device ID region of memory can be used to determine mask, variant and manufacturing information about the chip. The Device ID region is 2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled.
PIC24FJXXXGA0XX 6.2 Checksum Computation Checksums for the PIC24FJXXXGA0XX family are 16 bits in size.
PIC24FJXXXGA0XX TABLE 6-4: CHECKSUM COMPUTATION (CONTINUED) Read Code Protection Device PIC24FJ128GAGA006 PIC24FJ128GAGA008 PIC24FJ128GAGA010 Legend: Note: Checksum Computation Erased Checksum Value Checksum with 0xAAAAAA at 0x0 and Last Code Address Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE Enabled 0 0x0000 0x0000 Description Byte sum of
PIC24FJXXXGA0XX 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Standard Operating Conditions Operating Temperature: 0°C to +70°C. Programming at +25°C is recommended. Param Symbol No. Characteristic Min Max Units VDDCORE + 0.1 3.60 V D111 VDD Supply Voltage During Programming D112 IPP Programming Current on MCLR — 5 μA D113 IDDP Supply Current During Programming — 2 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.
PIC24FJXXXGA0XX NOTES: DS39768D-page 50 © 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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