Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 16-Bit 32 MHz I/O number 21

 2009-2013 Microchip Technology Inc. DS80000470H-page 1

PIC24FJ64GA004 FAMILY

The PIC24FJ64GA004 family devices that you have

received conform functionally to the current Device Data

Sheet (DS39881E), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC24FJ64GA004 family

silicon.

Data Sheet clarifications and corrections start on

Page 20, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC24FJ64GA004

family silicon revisions are shown in Tabl e 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (B8).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A3/A4B4B5B8

PIC24FJ64GA004 044Fh

3003h 3042h 3043h 3046h

PIC24FJ48GA004 044Eh

PIC24FJ32GA004 044Dh

PIC24FJ16GA004 044Ch

PIC24FJ64GA002 0447h

PIC24FJ48GA002 0446h

PIC24FJ32GA002 0445h

PIC24FJ16GA002 0444h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC24FJXXXGA0XX Flash Programming Specification” (DS39768) for detailed information

on Device and Revision IDs for your specific device.

PIC24FJ64GA004 Family

Silicon Errata and Data Sheet Clarification

Summary of content (24 pages)

PAGE 1
PIC24FJ64GA004 FAMILY PIC24FJ64GA004 Family Silicon Errata and Data Sheet Clarification The PIC24FJ64GA004 family devices that you have received conform functionally to the current Device Data Sheet (DS39881E), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC24FJ64GA004 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY Feature Item Number Affected Revisions(1) Issue Summary A3/A4 JTAG — 1. Persistent pull-up (RA3) when JTAG disabled. X LVD — 2. No LVD interrupt with low-voltage condition at Reset. X Core Idle mode 3. Clock failure trap fails in Idle mode. X Core Doze mode 4. RAM read repeats on entering Doze mode. X Core BOR 5. POR and BOR flags both set on BOR. X Core RAM 6. RAM size implementation on some devices. X A/D — 7.
PAGE 3
PIC24FJ64GA004 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature RTCC Item Number Affected Revisions(1) Issue Summary A3/A4 — 24. Write errors to ALCFGRPT register. 2 I C Slave mode 25. In Slave mode, ACKSTAT bit state change. X I2C — 26. Issues with write operations on I2CxSTAT. X B4 B5 B8 X UART IrDA® 27. IR baud clock only available during transmit. X I/O PPS 28. Issues with digital signal priorities with RP12 and RP18. X UART UERIF Interrupt 29.
PAGE 4
PIC24FJ64GA004 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature Item Number Affected Revisions(1) Issue Summary A3/A4 B4 B5 B8 X X X X X X X X X X X X SPI Master mode 46. Spurious transmission and reception of null data on wake-up from Sleep (Master mode). SPI Master mode 47. Inaccurate SPITBF flag with high clock divider. SPI Framed modes 48. Framed SPIx modes not supported. Core Data SRAM 49. Higher current consumption during SRAM operations.
PAGE 5
PIC24FJ64GA004 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B8). 3. Module: Core If a clock failure occurs when the device is in Idle mode, the oscillator failure trap does not vector to the Trap Service Routine.
PAGE 6
PIC24FJ64GA004 FAMILY 5. Module: Core 8. Module: A/D On a Brown-out Reset, both the BOR and POR bits may be set. This may cause the Brown-out Reset condition to be indistinguishable from the Power-on Reset. The A/D module will not generate code 511. Any conversion which should result in 511 normally, will instead generate 510 or 512. Work around None. None. Affected Silicon Revisions Affected Silicon Revisions A3/ A4 Work around B4 B5 B8 A3/ A4 B4 B5 B8 X X 9. Module: A/D 6.
PAGE 7
PIC24FJ64GA004 FAMILY 10. Module: I2C™ (I2C1, SDA Line State) 11. Module: UART When using I2C1, the SDA1 line state may not be detected properly unless it is first held low for 150 ns after enabling the I2C module. When the UARTx is in High-Speed mode, BRGH (UxMODE<3>) is set; some optimal UxBRG values can cause reception to fail. In Master mode, this error may cause a bus collision to occur instead of a Start bit transmission.
PAGE 8
PIC24FJ64GA004 FAMILY 14. Module: UART 17. Module: Output Compare With the auto-baud feature selected, the Sync field character (0x55) may be loaded into the FIFO as data. To prevent the Sync field character from being loaded into the FIFO, load the UxBRG register with either 0x0000 or 0xFFFF prior to enabling the auto-baud feature (ABAUD = 1).
PAGE 9
PIC24FJ64GA004 FAMILY 19. Module: SPI 20. Module: SPI In SPIx Slave mode (MSTEN = 0), with the slave select option enabled (SSEN = 1), the peripheral may accept transfers regardless of the SSx pin state. The received data in SPIxBUF will be accurate but not intended for the device. Work around There is a work around using the Peripheral Pin Select (PPS) feature.
PAGE 10
PIC24FJ64GA004 FAMILY 21. Module: I/O Ports The I/O pin outputs, VOL and VOH, meet the specifications in Table 3 below. Work around None. Affected Silicon Revisions A3/ A4 B4 B5 B8 X TABLE 3: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 Note 1: Min Typ(1) Max Units Conditions Output Low Voltage All I/O Pins VOH DO20 Characteristic Standard Operating Conditions: 2.0V to 3.
PAGE 11
PIC24FJ64GA004 FAMILY 22. Module: I/O Ports During Power-on Reset (POR), the device may drive the OSCO/RA3 pin as a clock out output for approximately 20 S. During this time, the pin will be driven high and low rather than being set to high-impedance. This may cause issues on designs that use the pin as a general purpose I/O. Designs should be reviewed to ensure that their intended operation will not be disrupted if the pin is driven during POR. Work around None.
PAGE 12
PIC24FJ64GA004 FAMILY 26. Module: I2C 28. Module: I/O (Peripheral Pin Select) Bit and byte-based operations may not have the intended affect on the I2CxSTAT register. It is possible for bit and byte operations, performed on the lower byte of I2CxSTAT, to clear the BCL bit (I2CxSTAT<10>). Bit and byte operation performed on the upper byte of I2CxSTAT, or on the BCL bit directly, may not be able to clear the BCL bit. Work around Modifications to the I2CxSTAT register should be done using word writes only.
PAGE 13
PIC24FJ64GA004 FAMILY 30. Module: UART (FIFO Error Flags) 32. Module: Core (Instruction Set) Under certain circumstances, the PERR and FERR error bits may not be correct for all bytes in the receive FIFO. This has only been observed when both of the following conditions are met: If an instruction producing a read-after-write stall condition is executed inside a REPEAT loop, the instruction will be executed fewer times than was intended.
PAGE 14
PIC24FJ64GA004 FAMILY 36. Module: I2C (Master Mode) 34. Module: RTCC Under certain circumstances, the value of the Alarm Repeat Counter (ALCFGRPT<7:0>) may be unexpectedly decremented. This happens only when a byte write to the upper byte of ALCFGRPT is performed in the interval between a device POR/BOR and the first edge from the RTCC clock source. Under certain circumstances, a module operating in Master mode may Acknowledge its own command addressed to a slave device.
PAGE 15
PIC24FJ64GA004 FAMILY 37. Module: I2C (Slave Mode) Under certain circumstances, a module operating in Slave mode may not respond correctly to some of the special addresses reserved by the I2C protocol. This happens when the following occurs: • 10-Bit Addressing mode is used (A10M = 1); and • bits, A<7:1>, of the slave address (I2CADD<7:1>) fall into the range of the reserved 7-bit address ranges: ‘1111xxx’ or ‘0000xxx’.
PAGE 16
PIC24FJ64GA004 FAMILY 42. Module: Core (Code Protection) When General Segment Code Protection has been enabled (GCP Configuration bit is programmed), applications are unable to write to the first 512 bytes of the program memory space (0000h through 0200h). In applications that may require the interrupt vectors to be changed during run time, such as bootloaders, modifications to the Interrupt Vector Tables (IVTs) will not be possible.
PAGE 17
PIC24FJ64GA004 FAMILY 46. Module: SPI (Master Mode) When operating in Enhanced Buffer Master mode, the module may transmit two bytes or two words of data with a value of 0h, immediately upon the microcontroller waking up from Sleep mode. At the same time, the module “receives” two words or two bytes of data, also with the value of 0h. The transmission of null data occurs even if the Transmit Buffer registers are empty prior to the microcontroller entering Sleep mode.
PAGE 18
PIC24FJ64GA004 FAMILY 51. Module: A/D Converter 52. Module: UART (Transmit Interrupt) Once the A/D module is enabled (AD1CON1<15> = 1), it may continue to draw extra current, even if the module is later disabled (AD1CON1<15> = 0). Work around In addition to disabling the module through the ADON bit, set the corresponding PMD bit (ADC1MD, PMD1<0>) to power it down completely.
PAGE 19
PIC24FJ64GA004 FAMILY 53. Module: I2C (SMBus) When the SMEN bit for the I2C2 module (I2C2CON<8>) is set to enable SMBus operation, the I2C1 module may not be able to communicate properly. The observed result is bus collisions on I2C1. Enabling SMBus operation on the I2C1 module has no impact on I2C2. Work around If both I2C modules and SMBus operation are required for an application, only use I2C1 for SMBus. Affected Silicon Revisions A3/ A4 B4 B5 B8 X X X X  2009-2013 Microchip Technology Inc.
PAGE 20
PIC24FJ64GA004 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39881E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None. DS80000470H-page 20  2009-2013 Microchip Technology Inc.
PAGE 21
PIC24FJ64GA004 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (5/2009) Initial release of this document; issued for Silicon Revision B5.
PAGE 22
PIC24FJ64GA004 FAMILY Rev F Document (11/2011) Added silicon issue 52 (UART – Transmit Interrupt) to Revisions B4, B5 and B8. Added silicon issue 53 (I2C – SMBus) to all silicon revisions. Rev G Document (2/2013) Updated the minimum VBOR specification (DC18) in data sheet clarification #2 to 1.8V (previously 1.96V). Rev H Document (5/2013) Updated data sheet revision level to E. Removed all existing data sheet clarifications, as they are addressed in the new revision of the data sheet.
PAGE 23
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 24
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