Datasheet
2010-2013 Microchip Technology Inc. DS39881E-page 241
PIC24FJ64GA004 FAMILY
DI31 IPU Maximum Load Current
for Digital High Detection
with Internal Pull-up
——30µAVDD = 2.0V
——100µAV
DD = 3.3V
I
IL Input Leakage Current
(2,3)
DI50 I/O Ports — — +1 AVSS VPIN VDD,
Pin at high-impedance
DI51 Analog Input Pins — — +
1 AVSS VPIN VDD,
Pin at high-impedance
DI55 MCLR
——+1 AVSS VPIN VDD
DI56 OSCI — — +1 AVSS VPIN VDD,
XT and HS modes
I
ICL Input Low Injection
Current
DI60a 0 — -5
(5,8)
mA All pins except VDD, VSS,
AV
DD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO,
D+, D-, VUSB, and VBUS
IICH Input High Injection
Current
DI60b 0 — +5
(6,7,8)
mA All pins except VDD, VSS,
AV
DD, AVSS, MCLR, VCAP,
RB11, SOSCI, SOSCO,
D+, D-, VUSB, and VBUS,
and all 5V tolerant pins
(7)
IICT Total Input Injection
Current
DI60c (sum of all I/O and control
pins)
-20(9) — +20
(9)
mA Absolute instantaneous
sum of all ± input injection
currents from all I/O pins
(| I
ICL + | IICH |) IICT)
TABLE 27-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C T
A +125°C for Extended
Param
No.
Sym Characteristic Min Typ
(1)
Max Units Conditions
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR
pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Refer to Table 1-2 for I/O pin buffer types.
5: Parameter is characterized but not tested.
6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources greater
than 5.5V.
8: Injection currents > | 0 | can affect the performance of all analog peripherals (e.g., A/D, comparators,
internal band gap reference, etc.)
9: Any number and/or combination of I/O pins not excluded under I
ICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.