Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 212  2010-2013 Microchip Technology Inc.
REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2
U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1
— — — — — — — —
bit 23 bit 16
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
IESO WUTSEL1
(1)
WUTSEL0
(1)
SOSCSEL1
(1)
SOSCSEL0
(1)
FNOSC2 FNOSC1 FNOSC0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 r R/PO-1 R/PO-1 R/PO-1
FCKSM1 FCKSM0 OSCIOFCN IOL1WAY
r I2C1SEL POSCMD1 POSCMD0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 23-16 Unimplemented: Read as ‘1’
bit 15 IESO: Internal External Switchover bit
1 = IESO mode (Two-Speed Start-up) is enabled
0 = IESO mode (Two-Speed Start-up) is disabled
bit 14-13 WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits
(1)
11 = Default regulator start-up time is used
01 = Fast regulator start-up time is used
x0 = Reserved; do not use
bit 12-11 SOSCSEL<1:0>: Secondary Oscillator Power Mode Select bits
(1)
11 = Default (High Drive Strength) mode
01 = Low-Power (Low Drive Strength) mode
x0 = Reserved; do not use
bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits
111 = Fast RC Oscillator with Postscaler (FRCDIV)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits
1x = Clock switching and Fail-Safe Clock Monitor are disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 OSCIOFCN: OSCO Pin Configuration bit
If POSCMD<1:0> =
11 or 00:
1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2)
0 = OSCO/CLKO/RA3 functions as port I/O (RA3)
If POSCMD<1:0> =
10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RA3.
Note 1: These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV regis-
ter value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet
for the location and interpretation of product date codes.