Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 268  2010-2013 Microchip Technology Inc.
APPENDIX B: ADDITIONAL
GUIDANCE FOR
PIC24FJ64GA004
FAMILY
APPLICATIONS
B.1 Additional Methods for Power
Reduction
Devices in the PIC24FJ64GA004 family include a num-
ber of core features to significantly reduce the applica-
tion’s power requirements. For truly power-sensitive
applications, it is possible to further reduce the
application’s power demands by taking advantage of
the device’s regulator architecture. These methods
help decrease power in two ways: by disabling the
internal voltage regulator to eliminate its power con-
sumption, and by reducing the voltage on V
DDCORE to
lower the device’s dynamic current requirements.
Using these methods, it is possible to reduce Sleep
currents (I
PD) from 3.5 A to 250 nA (typical values,
refer to Parameters DC60d and DC60g in Tabl e 2 7 - 6).
For dynamic power consumption, the reduction in
V
DDCORE from 2.5V provided by the regulator, to 2.0V,
can provide a power reduction of about 30%.
When using a regulated power source or a battery with
a constant output voltage, it is possible to decrease
power consumption by disabling the regulator. In this
case (Figure B-1), a simple diode can be used to
reduce the voltage from 3V or greater to the 2V-2.5V
required for V
DDCORE. This method is only advised on
power supplies, such as Lithium Coin cells, which
maintain a constant voltage over the life of the battery.
FIGURE B-1: POWER REDUCTION
EXAMPLE FOR CONSTANT
VOLTAGE SUPPLIES
A similar method can be used for non-regulated
sources (Figure B-2). In this case, it can be beneficial
to use a low quiescent current, external voltage regula-
tor. Devices, such as the MCP1700, consume only
1 A to regulate to 2V or 2.5V, which is lower than the
current required to power the internal voltage regulator.
FIGURE B-2: POWER REDUCTION
EXAMPLE FOR
NON-REGULATED SUPPLIES
VDD
DISVREG
V
DDCORE
VSS
PIC24FJ64GA
3.0V
D1
Coin Cell
2.3V
VDD
DISVREG
V
DDCORE
VSS
PIC24FJ64GA
3.3V
‘AA’
MCP1700
2.0V