Datasheet

 2010-2013 Microchip Technology Inc. DS39881E-page 213
PIC24FJ64GA004 FAMILY
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK (OSCCON<6>) bit can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK (OSCCON<6>) bit can be set and cleared as needed, provided the unlock sequence
has been completed
bit 3 Reserved
bit 2 I2C1SEL: I2C1 Pin Select bit
1 = Use default SCL1/SDA1 pins
0 = Use alternate SCL1/SDA1 pins
bit 1-0 POSCMD<1:0:> Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
Note 1: These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV regis-
ter value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet
for the location and interpretation of product date codes.
REGISTER 24-3: DEVID: DEVICE ID REGISTER
UUUUUUUU
— — — — — — — —
bit 23 bit 16
UURRRRRR
— — FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2
bit 15 bit 8
RRRRRRRR
FAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-14 Unimplemented: Read as ‘1’
bit 13-6 FAMID<7:0>: Device Family Identifier bits
00010001 = PIC24FJ64GA004 family
bit 5-0 DEV<5:0>: Individual Device Identifier bits
000100 = PIC24FJ16GA002
000101 = PIC24FJ32GA002
000110 = PIC24FJ48GA002
000111 = PIC24FJ64GA002
001100 = PIC24FJ16GA004
001101 = PIC24FJ32GA004
001110 = PIC24FJ48GA004
001111 = PIC24FJ64GA004