Datasheet

 2010-2013 Microchip Technology Inc. DS39881E-page 129
PIC24FJ64GA004 FAMILY
FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
FIGURE 12-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TON
TCKPS<1:0>
2
T
CY
TCS
(1)
TGATE
(1)
Gate
T2CK
Sync
PR2 (PR4)
Set T2IF (T4IF)
Equal
Comparator
Reset
Q
QD
CK
TGATE
1
0
(T4CK)
Sync
Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
1x
01
00
Prescaler
1, 8, 64, 256
TMR2 (TMR4)
TON
TCKPS<1:0>
2
T
CY
TCS
(1)
TGATE
(1)
T3CK
PR3 (PR5)
Set T3IF (T5IF)
Equal
Comparator
TMR3 (TMR5)
Reset
TGATE
1
0
A/D Event Trigger
(2)
(T5CK)
Prescaler
1, 8, 64, 256
Sync
Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
2: The A/D Event Trigger is available only on Timer3.
1x
01
00
Q
QD
CK