Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 128  2010-2013 Microchip Technology Inc.
FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
Set T3IF (T5IF)
Equal
Comparator
Reset
LSBMSB
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see
Section 10.4 “Peripheral Pin Select (PPS)” for more information.
3: The A/D Event Trigger is available only on Timer2/3.
Data Bus<15:0>
Read TMR2 (TMR4)
(1)
Write TMR2 (TMR4)
(1)
16
16
16
Q
QD
CK
TGATE
0
1
TON
TCKPS<1:0>
2
T
CY
TCS
(2)
TGATE
(2)
T2CK
Sync
A/D Event Trigger
(3)
(T4CK)
1x
01
00
Gate
Sync
Prescaler
1, 8, 64, 256
PR3 PR2
(PR5) (PR4)
TMR3HLD
(TMR5HLD)
TMR3
TMR2
(TMR5)
(TMR4)