Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 16-Bit 32 MHz I/O number 19

PIC24FJ64GB004

DS80000487K-page 8  2009-2013 Microchip Technology Inc.

19. Module: USB (Device Mode)

In previous literature for this module, the

EPSTALL bits (U1EPn<1>) are described as

being only stall status indicator bits in Device

mode. In actual implementation, the EPSTALL

bits function as both status and control bits.

If the EPSTALL bit for Endpoint ‘n’ is set (either

by the SIE hardware or manually in firmware),

both the IN and OUT endpoints, associated with

the endpoint, will send STALL packets when the

endpoint’s UOWN bit (BDnSTAT<15>) is also

set.

Work around

For Host Applications: No work around is

needed as hosts do not send STALL packets.

For Device Mode Applications: When it is neces-

sary to stop sending STALL packets on an

endpoint, clear the endpoint’s respective

BSTALL (BDnSTAT<10>) and EPSTALL bits. If

the application firmware was developed based

on one of the examples in the Microchip USB

framework, this is already the default behavior of

the USB stack firmware (except Version 2.8); no

further work around is normally needed.

If a Device mode application was based upon

Version 2.8 of the USB framework, and the

application uses STALL packets on any of the

application endpoints (1-15), it is suggested to

update the application to the latest version.

Affected Silicon Revisions

20. Module: RTCC

Under certain circumstances, the RTCC may not

be clocked properly when the device is in Deep

Sleep mode. This is observed only when all of the

following are true:

• The RTCC is using the LPRC as its clock

source (RTCOSC = 0);

• The SOSC clock source is disabled

(SOSCSEL<1:0> = 00); and

• RA4 is in a logic low state during entry into

Deep Sleep, either by being driven low as

an output (TRISA4 and LATA4 are both ‘0’),

or being held low as an input.

Work around

The issue does not occur if RA4 is maintained in a

logic high state while the device is in Deep Sleep.

This can be done by driving the pin high as an

output (TRISA4 = 0, LATA4 = 1) or driving the pin

to logic high from an external source while it is

configured as an input.

The issue also does not occur if the SOSC is

configured for one of the Crystal Driver modes

(SOSCSEL<1:0> = x1).

Either method can be used with the same effect.

Affected Silicon Revisions