Information

PIC24FJ64GB004
DS80000487K-page 6  2009-2013 Microchip Technology Inc.
13. Module: Interrupts (INTx)
Writing to the INTCON2 register may cause an
external interrupt event (inputs on INT0 through
INT2) to be missed. This only happens when the
interrupt event and the write event occur during
the same clock cycle.
Work around
If this cannot be avoided, write the data intended
for INTCON2 to any other register in the inter-
rupt block of the SFR (addresses 0080h to
00E0h); then write the data to INTCON2.
Be certain to write the data to a register not
being actively used by the application, or to any
of the interrupt flag registers, in order to avoid
spurious interrupts. For example, if the inter-
rupts controlled by IEC4 are not being used in
the application, the code sequence would be:
IEC4 = 0x1E;
INTCON2 = 0x1E;
IEC4 = 0;
It is the user’s responsibility to determine an
appropriate register for the particular application.
Affected Silicon Revisions
14. Module: Oscillator
The POSCEN bit (OSCCON<2>) has no effect
when a Primary Oscillator with PLL mode is
selected (COSC<2:0> = 011). If XTPLL, HSPLL
or ECPLL Oscillator mode is selected, and the
device enters Sleep mode, the Primary Oscilla-
tor will be disabled, regardless of the state of the
POSCEN bit.
XT, HS and EC Oscillator modes (without the
PLL) will continue to operate as expected.
Work around
None.
Affected Silicon Revisions
15. Module: A/D Converter
Once the A/D module is enabled
(AD1CON1<15> = 1), it may continue to draw
extra current, even if the module is later disabled
(AD1CON1<15> = 0).
Work around
In addition to disabling the module through the
ADON bit, set the corresponding PMD bit
(ADC1MD, PMD1<0>) to power it down
completely.
Disabling the A/D module through the PMD reg-
ister also disables the AD1PCFG registers,
which in turn, affects the state of any port pins
with analog inputs. Users should consider the
effect on I/O ports and other digital peripherals
on those ports when ADC1MD is used for power
conservation.
Affected Silicon Revisions
16. Module: Output Compare (Interrupt)
Under certain circumstances, an output com-
pare match may cause the Output Compare
Interrupt Flag (OCxIF) to become set prior to the
Change-of-State (COS) of the OCx pin. This has
been observed when all of the following are true:
• the module is in One-Shot mode
(OCM<2:0> = 001, 010 or 100);
• one of the timer modules is being used as
the time base; and
• a timer prescaler other than 1:1 is selected.
If the module is re-initialized by clearing
OCM<2:0> after the One-Shot compare, the
OCx pin may not be driven as expected.
Work around
After OCxIF is set, allow an interval (in CPU
cycles) of at least twice the prescaler factor to
elapse before clearing OCM<2:0>. For
example, for a prescaler value of 1:8, allow
16 CPU cycles to elapse after the interrupt.
Affected Silicon Revisions
A2
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A2
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A2
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A2
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