Information
2009-2013 Microchip Technology Inc. DS80000487K-page 5
PIC24FJ64GB004
9. Module: Triple (Enhanced) Comparator
When any of the internal band gap options (VBG,
V
BG/2 or VBG/6) are selected by the voltage refer-
ence module as the comparator’s CV
REF- input,
the comparator may not generate an interrupt
when a preprogrammed event is detected.
The CV
REF+ input works as previously
described.
Work around
If it is necessary to use the internal band gap as
a reference, do the following:
1. Enable the comparator’s output
(CMCON<14> = 1) and map the output to a
pin with CN functionality or map an INTx
function to this same pin. This method only
consumes one I/O pin and requires no
external connections.
2. Monitor the pin for an interrupt event.
Affected Silicon Revisions
10. Module: Core (Doze Mode)
Operations that immediately follow any manipu-
lations of the DOZE<2:0> or DOZEN bits
(CLKDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this
interval.
Work around
Always insert a NOP instruction before and after
either of the following:
• Enabling or disabling Doze mode by setting
or clearing the DOZEN bit
• Before or after changing the DOZE<2:0> bits
Affected Silicon Revisions
11. Module: Oscillator (Two-Speed Start-up)
Two-Speed Start-up is not functional. Leaving
the IESO Configuration bit in its default state
(Two-Speed Start-up enabled) may result in
unpredictable operation.
Work around
None. Always program the IESO Configuration
bit to disable the feature (CW2<15> = 0).
Affected Silicon Revisions
12. Module: A/D Converter
When using PGEC3 and PGED3 to debug an
application, all voltage references will be disabled.
This includes VREF+, VREF-, AVDD and AVSS. Any
A/D conversion will always equal 03FFh.
Work around
Use either PGEC1/PGED1 or PGEC2/PGED2
to debug any A/D functionality.
Affected Silicon Revisions
A2
X
A2
X
A2
X
A2
X