Information

PIC24FJ64GB004
DS80000487K-page 2  2009-2013 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A2
Output
Compare
Cascaded
mode
1. Cascaded mode does not work as expected. X
Power-
Saving Modes
Sleep mode 2. Transitory increase in I
PD under certain conditions. X
USB — 3. Issue with Host mode, low-speed operation. X
USB — 4. CRC errors while using external transceiver. X
UART Break
Character
Generation
5. Will not generate back-to-back Break characters. X
Oscillator Secondary
Oscillator
Configuration
6. High-current draw when external signal applied under
certain conditions.
X
SPI Master mode 7. Spurious transmission and reception of null data on
wake-up from Sleep (Master mode).
X
SPI Master mode 8. Inaccurate SPITBF flag with high clock divider. X
Triple
(Enhanced)
Comparator
— 9. No interrupt generation with internal band gap reference. X
Core Doze Mode 10. Instruction execution glitches following Doze bit changes. X
Oscillator Two-Speed
Start-up
11. Feature is not functional. X
A/D Converter — 12. Disabled voltage references during Debug mode. X
Interrupts INTx 13. External interrupts missed when writing to INTCON2. X
Oscillator — 14. POSCEN bit does not work with Primary + PLL modes X
A/D Converter — 15. Module continues to draw current when disabled. X
Output
Compare
Interrupt 16. Interrupt flag may precede the output pin change under
certain circumstances.
X
UART Transmit 17. A TX Interrupt may occur before the data transmission is
complete.
X
USB Device and
Host Modes
18. ACTVIF wake-up behavior differs from previous
documentation.
X
USB Device Mode 19. EPSTALL bit behavior differs from previous documentation. X
RTCC LPRC Clock
Source
20. LPRC does not clock RTCC in Deep Sleep, under certain
circumstances.
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.