Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 98  2010-2013 Microchip Technology Inc.
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 =
0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
bit 6 IOLOCK: I/O Lock Enable bit
(2)
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit
(3)
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 Unimplemented: Read as ‘0’
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 2 Unimplemented: Read as ‘0’
bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enables Secondary Oscillator
0 = Disables Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiates an oscillator switch to a clock source specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits.
2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.
3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.