Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 8  2010-2013 Microchip Technology Inc.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between devices with
the same pin count, or even jumping from 28-pin to
44-pin devices.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
1.2 Other Special Features
• Communications: The PIC24FJ64GA004 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I
2
C
modules that support both Master and Slave
modes of operation. Devices also have, through
the Peripheral Pin Select (PPS) feature, two
independent UARTs with built-in IrDA
encoder/decoders and two SPI modules.
• Peripheral Pin Select (PPS): The Peripheral Pin
Select feature allows most digital peripherals to
be mapped over a fixed set of digital I/O pins.
Users may independently map the input and/or
output of any one of the many digital peripherals
to any one of the I/O pins.
• Parallel Master/Enhanced Parallel Slave Port:
One of the general purpose I/O ports can be
reconfigured for enhanced parallel data communi-
cations. In this mode, the port can be configured
for both master and slave operations, and
supports 8-bit and 16-bit data transfers with up to
16 external address lines in Master modes.
• Real-Time Clock/Calendar (RTCC): This module
implements a full-featured clock and calendar with
alarm functions in hardware, freeing up timer
resources and program memory space for use of
the core application.
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period, as
well as faster sampling speeds.
1.3 Details on Individual Family
Members
Devices in the PIC24FJ64GA004 family are available
in 28-pin and 44-pin packages. The general block
diagram for all devices is shown in Figure 1-1.
The devices are differentiated from each other in two
ways:
1. Flash program memory (64 Kbytes for
PIC24FJ64GA devices, 48 Kbytes for
PIC24FJ48GA devices, 32 Kbytes for
PIC24FJ32GA devices and 16 Kbytes for
PIC24FJ16GA devices).
2. Internal SRAM memory (4k for PIC24FJ16GA
devices, 8k for all other devices in the family).
3. Available I/O pins and ports (21 pins on 2 ports
for 28-pin devices and 35 pins on 3 ports for
44-pin devices).
All other features for devices in this family are identical.
These are summarized in Ta bl e 1 -1.
A list of the pin features that are available on the
PIC24FJ64GA004 family devices, sorted by function, is
shown in Tabl e 1-2. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the pinout diagrams in the beginning of
the data sheet. Multiplexed features are sorted by the
priority given to a feature, with the highest priority
peripheral being listed first.