Datasheet

PIC24FJ64GA004 FAMILY
DS39881E-page 16  2010-2013 Microchip Technology Inc.
T1CK 12 9 34 I ST Timer1 Clock.
TCK 17 14 13 I ST JTAG Test Clock Input.
TDI 21 18 35 I ST JTAG Test Data Input.
TDO 18 15 32 O — JTAG Test Data Output.
TMS 22 19 12 I ST JTAG Test Mode Select Input.
V
DD 13, 28 10, 25 28, 40 P — Positive Supply for Peripheral Digital Logic and I/O Pins.
V
DDCAP 20 17 7 P — External Filter Capacitor Connection (regulator enabled).
V
DDCORE 20 17 7 P — Positive Supply for Microcontroller Core Logic (regulator
disabled).
V
REF- 3 28 20 I ANA A/D and Comparator Reference Voltage (low) Input.
V
REF+ 2 27 19 I ANA A/D and Comparator Reference Voltage (high) Input.
V
SS 8, 27 5, 24 29, 39 P — Ground Reference for Logic and I/O Pins.
TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O
Input
Buffer
Description
28-Pin
SPDIP/
SSOP/SOIC
28-Pin
QFN
44-Pin
QFN/TQFP
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C™ = I
2
C/SMBus input buffer
Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.