Datasheet

 2010-2013 Microchip Technology Inc. DS39881E-page 155
PIC24FJ64GA004 FAMILY
bit 5 ACKDT: Acknowledge Data bit (when operating as I
2
C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends a NACK during Acknowledge
0 = Sends an ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I
2
C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
Hardware is clear at the end of master Acknowledge sequence.
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I
2
C master)
1 = Enables Receive mode for I
2
C. Hardware is clear at the end of eighth bit of master receive data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I
2
C master)
1 = Initiates Stop condition on SDAx and SCLx pins. Hardware is clear at the end of master Stop sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I
2
C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware is clear at the end of master
Repeated Start sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I
2
C master)
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at the end of master Start sequence.
0 = Start condition is not in progress
REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
Note 1: In Slave mode, the module will not automatically clock stretch after receiving the address byte.