Datasheet

PIC24FJ256GB210 FAMILY
DS39975A-page 270  2010 Microchip Technology Inc.
TABLE 19-2: PARALLEL MASTER PORT PIN DESCRIPTION
Pin Name Type Description
PMA<22:16>
(1)
O Address Bus Bits<22-16>
PMA<15>, PMCS2
O Address Bus Bit<15>
O Chip Select 2 (alternate location)
I/O Data Bus Bit<15> when port size is 16 bits and address is
multiplexed
PMA<14>, PMCS1
O Address Bus Bit<14>
O Chip Select 1 (alternate location)
I/O Data Bus Bit<14> when port size is 16-bit and address is
multiplexed
PMA<13:8>
O Address Bus Bits<13-8>
I/O Data Bus Bits<13-8> when port size is 16 bits and address
is multiplexed
PMA<7:3> O Address Bus Bits<7-3>
PMA<2>, PMALU
(1)
O Address Bus Bit<2>
O Address latch upper strobe for multiplexed address
PMA<1>, PMALH
I/O Address Bus Bit<1>
O Address latch high strobe for multiplexed address
PMA<0>, PMALL
I/O Address Bus Bit<0>
O Address latch low strobe for multiplexed address
PMD<15:8> I/O Data Bus Bits<15-8> when address is not multiplexed
PMD<7:4>
I/O Data Bus Bits<7-4>
O Address Bus Bits<7-4> when port size is 4 bits and address
is multiplexed with 1 address phase
PMD<3:0> I/O Data Bus Bits<3-0>
PMCS1 I/O Chip Select 1
PMCS2 O Chip Select 2
PMWR, PMENB I/O Write strobe or enable signal depending on Strobe mode
PMRD, PMRD/PMWR
I/O Read strobe or Read/Write signal depending on Strobe
mode
PMBE1
(1)
O Byte indicator
PMBE0 O Nibble or byte indicator
PMACK1 I Acknowledgment 1
PMACK2 I Acknowledgment 2
Note 1: Available only in 100-pin devices (PIC24FJXXXGB210).