Datasheet
2010 Microchip Technology Inc. DS39975A-page 269
PIC24FJ256GB210 FAMILY
19.0 ENHANCED PARALLEL
MASTER PORT (EPMP)
The Enhanced Parallel Master Port (EPMP) module
provides a parallel 4-bit (Master mode only), 8-bit (Mas-
ter and Slave modes) or 16-bit (Master mode only) data
bus interface to communicate with off-chip modules,
such as memories, FIFOs, LCD controllers and other
microcontrollers. This module can serve as either the
master or the slave on the communication bus. For
EPMP Master modes, all external addresses are
mapped into the internal Extended Data Space (EDS).
This is done by allocating a region of the EDS for each
chip select, and then assigning each chip select to a
particular external resource, such as a memory or
external controller. This region should not be assigned
to another device resource, such as RAM or SFRs. To
perform a write or read on an external resource, the
CPU should simply perform a write or read within the
address range assigned for EPMP.
Key features of the EPMP module are:
• Extended Data Space (EDS) Interface allows
Direct Access from the CPU
• Up to 23 Programmable Address Lines
• Up to 2 Chip Select Lines
• Up to 2 Acknowledgement Lines (one per chip
select)
• 4-Bit, 8-Bit or 16-Bit Wide Data Bus
• Programmable Strobe Options (per chip select)
- Individual Read and Write Strobes or;
- Read/Write
Strobe with Enable Strobe
• Programmable Address/Data Multiplexing
• Programmable Address Wait States
• Programmable Data Wait States (per chip select)
• Programmable Polarity on Control Signals (per
chip select)
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
19.1 ALTPMP Setting
Many of the lower order EPMP address pins are shared
with ADC inputs. This is an untenable situation for
users that need both the ADC channels and the EPMP
bus. If the user does not need to use all the address
bits, then by clearing the ALTPMP
(CW3<12>) Config-
uration bit, the lower order address bits can be mapped
to higher address pins, which frees the ADC channels.
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 42. “Enhanced Parallel Master
Port (EPMP)” (DS39730). The informa-
tion in this data sheet supersedes the
information in the FRM.
Note: The alternate PMP pin selection is not
available in 64-pin devices
(PIC24FJXXXGB206) and so the
Configuration bit, ALTPMP, is also not
available.
TABLE 19-1: ALTERNATE EPMP PINS
(1)
Pin ALTPMP = 0 ALTPMP = 1
RA14 PMCS2 PMA22
RC4 PMA22 PMCS2
RF12 PMA5 PMA18
RG6 PMA18 PMA5
RG7 PMA20 PMA4
RA3 PMA4 PMA20
RG8 PMA21 PMA3
RA4 PMA3 PMA21
Note 1: The alternate EPMP pins are valid only for 100-pin devices (PIC24FJXXXGB210).