Datasheet
PIC24FJ256GB210 FAMILY
DS39975A-page 24 2010 Microchip Technology Inc.
PMA0 30 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
PMA1 29 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
PMA2 8 14 F3 O —
Parallel Master Port Address bits<22:2>.
PMA3 6 12, 60
(1)
F2, G11
(1)
O—
PMA4 5 11,59
(1)
F4,G10
(1)
O—
PMA5 4 10,40
(1)
E3,K6
(1)
O—
PMA6 16 29 K3 O —
PMA7 22 28 L2 O —
PMA8 32 50 L11 O —
PMA9 31 49 L10 O —
PMA10 28 42 L7 O —
PMA11 27 41 J7 O —
PMA12 24 35 J5 O —
PMA13 23 34 L5 O —
PMA14 45 71 C11 O —
PMA15 44 70 D11 O —
PMA16 — 95 C4 O —
PMA17 — 92 B5 O —
PMA18 — 40,10
(1)
K6,E3
(1)
O—
PMA19 — 19 G2 O —
PMA20 — 59, 11
(1)
G10, F4
(1)
O—
PMA21 — 60,12
(1)
G11,F2
(1)
O—
PMA22 — 66,9
(1)
E11,E1
(1)
O—
PMACK1 50 77 A10 I ST/TTL Parallel Master Port Acknowledge Input 1.
PMACK2 43 69 E10 I ST/TTL Parallel Master Port Acknowledge Input 2.
PMALL 30 44 L8 O — Parallel Master Port Lower Address Latch Strobe.
PMALH 29 43 K7 O — Parallel Master Port Higher Address Latch Strobe.
PMALU — 14 F3 O — Parallel Master Port Upper Address Latch Strobe.
PMBE0 51 78 B9 O — Parallel Master Port Byte Enable Strobe 0.
PMBE1 — 67 E8 O — Parallel Master Port Byte Enable Strobe 1.
PMCS1 45 71
(3)
,18 C11
(3)
,G1 I/O ST/TTL Parallel Master Port Chip Select Strobe 1.
PMCS2 44 70
(2)
,9,
66
(1)
D11
(2)
,E1,
E11
(1)
O — Parallel Master Port Chip Select Strobe 2.
TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O
Input
Buffer
Description
64-Pin
TQFP/QFN
100-Pin
TQFP
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C™ = I
2
C/SMBus input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
(CW3<12>) bit is programmed to ‘0’.
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.