Datasheet
2010 Microchip Technology Inc. DS39975A-page 23
PIC24FJ256GB210 FAMILY
CN81 — 95 C4 I ST
Interrupt-on-Change Inputs.
CN82 — 1 B2 I ST
CN83 37 57 H10 I ST
CN84 36 56 J11 I ST
CTEDG1 28 42 L7 I ANA CTMU External Edge Input 1.
CTEDG2 27 41 J7 I ANA CTMU External Edge Input 2.
CTPLS 29 43 K7 O — CTMU Pulse Output.
CV
REF 23 34 L5 O — Comparator Voltage Reference Output.
D+ 37 57 H10 I/O — USB Differential Plus Line (internal transceiver).
D- 36 56 J11 I/O — USB Differential Minus Line (internal transceiver).
DMH 46 72 D9 O — D- External Pull-up Control Output.
DMLN 42 68 E9 O — D- External Pull-down Control Output.
DPH 50 77 A10 O — D+ External Pull-up Control Output.
DPLN 43 69 E10 O — D+ External Pull-down Control Output.
ENVREG 57 86 J7 I ST Voltage Regulator Enable.
INT0 46 72 D9 I ST External Interrupt Input.
MCLR
7 13 F1 I ST Master Clear (device Reset) Input. This line is brought low
to cause a Reset.
OSCI 39 63 F9 I ANA Main Oscillator Input Connection.
OSCO 40 64 F11 O ANA Main Oscillator Output Connection.
PGEC1 15 24 K1 I/O ST In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1.
PGED1 16 25 K2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 1.
PGEC2 17 26 L1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 2.
PGED2 18 27 J3 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 2.
PGEC3 11 20 H1 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock 3.
PGED3 12 21 H2 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data 3.
TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Function
Pin Number
I/O
Input
Buffer
Description
64-Pin
TQFP/QFN
100-Pin
TQFP
121-Pin
BGA
Legend: TTL = TTL input buffer ST = Schmitt Trigger input buffer
ANA = Analog level input/output I
2
C™ = I
2
C/SMBus input buffer
Note 1: The alternate EPMP pins are selected when the ALTPMP
(CW3<12>) bit is programmed to ‘0’.
2: The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF<1:0> = 01 or 10.
3: The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF<1:0> = 10.
4: The alternate V
REF pins selected when the ALTVREF (CW1<5>) bit is programmed to ‘0’.