Datasheet

 2010 Microchip Technology Inc. DS39975A-page 145
PIC24FJ256GB210 FAMILY
FIGURE 8-2: 96 MHz PLL BLOCK
8.5.1 SYSTEM CLOCK GENERATION
The system clock is generated from the 96 MHz branch
using a configurable postscaler/divider to generate a
range of frequencies for the system clock multiplexer.
The output of the multiplexer is further passed through
a fixed divide-by-3 divider and the final output is used
as the system clock. Figure 8-2 shows this logic in the
system clock sub-block. Since the source is a 96 MHz
signal, the possible system clock frequencies are listed
in Table 8-2. The available system clock options are
always the same, regardless of the setting of the
PLLDIV Configuration bits.
TABLE 8-2: SYSTEM CLOCK OPTIONS FOR 96 MHz PLL BLOCK
PLL
96 MHz
PLL
 3
 2
Prescaler
4 MHz
PLL
Prescaler
48 MHz Clock
for USB Module
PLL Output
for System Clock
CPDIV<1:0>
PLLDIV<2:0>
Input from
POSC
Input from
FRC
FNOSC<2:0>
(4 MHz or
8 MHz)
00
01
10
11
32 MHz
111
110
101
100
011
010
001
000
 12
 8
 8
 6
 5
 4
 3
 2
 1
 4
 2
 1
MCU Clock Division
(CPDIV<1:0>)
System Clock Frequency
(Instruction Rate in MIPS)
None (00)32MHz (16)
2 (01)16MHz (8)
4 (10)8MHz (4)
(1)
8 (11)4MHz (2)
(1)
Note 1: These options are not compatible with USB operation. They may be used whenever the PLL branch is
selected and the USB module is disabled.