PIC24FJ256GB210 Family Data Sheet 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC24FJ256GB210 FAMILY 64/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Universal Serial Bus Features: Peripheral Features (Continued): • USB v2.0 On-The-Go (OTG) Compliant • Dual Role Capable – Can act as either Host or Peripheral • Low-Speed (1.
PIC24FJ256GB210 FAMILY High-Performance CPU Analog Features: • • • • • • • • 10-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Operation is possible in Sleep mode - Band gap reference input feature • Three Analog Comparators with Programmable Input/Output Configuration • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Minimum time measurement setting at 100 ps • Available LVD Interrupt VLVD Level Modified Harvar
PIC24FJ256GB210 FAMILY 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/SESSVLD/CN69/RF1 VBUSST/VCMPST1/VBUSVLD/CN68/RF0 ENVREG VCAP C3INA/SESSEND/CN16/RD7 C3INB/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 RP22/PMBE0/CN52/RD3 DPH/RP23/PMACK1/CN51/RD2 VCPCON/RP24/VBUSCHG/CN50/RD1 Pin Diagram (64-Pin TQFP/QFN) PMD5/CN63/RE5 1 SCL3/PMD6/CN64/RE6 2 SDA3/PMD7/CN65/RE7 3 C1IND/RP21/PMA5/CN8/RG6 4 C1INC/RP26/PMA4/CN9/RG7 5
PIC24FJ256GB210 FAMILY TABLE 1: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Pin Function Pin Function 1 PMD5/CN63/RE5 33 RP16/USBID/CN71/RF3 2 SCL3/PMD6/CN64/RE6 34 VBUS/RF7 3 SDA3/PMD7/CN65/RE7 35 VUSB 4 C1IND/RP21/PMA5/CN8/RG6 36 D-/CN84/RG3 5 C1INC/RP26/PMA4/CN9/RG7 37 D+/CN83/RG2 6 C2IND/RP19/PMA3/CN10/RG8 38 VDD 7 MCLR 39 OSCI/CLKI/CN23/RC12 8 C2INC/RP27/PMA2/CN11/RG9 40 OSCO/CLKO/CN22/RC15 9 VSS 41 VSS 10 VDD 42 RTCC/DMLN/RP2/CN53/RD8 11 PGEC3/A
PIC24FJ256GB210 FAMILY PMD2/CN60/RE2 CN80/RG13 CN79/RG12 PMA16/CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 AN22/PMA17/CN40/RA7 AN23/CN39/RA6 PMD8/CN77/RG0 PMD9/CN78/RG1 VCMPST2/SESSVLD/PMD10/CN69/RF1 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 ENVREG VCAP C3INA/SESSEND/PMD15/CN16/RD7 C3INB/PMD14/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 PMD13/CN19/RD13 RPI42/PMD12/CN57/RD12 RP22/PMBE0/CN52/RD3 DPH/RP23/PMACK1/CN51/RD2 VCPCON/RP24/VBUSCHG/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79
PIC24FJ256GB210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Pin Function Pin Function 1 CN82/RG15 41 AN12/PMA11/CTEDG2/CN30/RB12 2 VDD 42 AN13/PMA10/CTEDG1/CN31/RB13 3 PMD5/CN63/RE5 43 AN14/CTPLS/RP14/PMA1/CN32/RB14 4 SCL3/PMD6/CN64/RE6 44 AN15/REFO/RP29/PMA0/CN12/RB15 5 SDA3/PMD7/CN65/RE7 45 VSS 6 RPI38/CN45/RC1 46 VDD 7 RPI39/CN46/RC2 47 RPI43/CN20/RD14 8 RPI40/CN47/RC3 48 RP5/CN21/RD15 9 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 49 RP10/PMA9/CN
PIC24FJ256GB210 FAMILY TABLE 2: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES (CONTINUED) Pin Function Pin Function 81 RP25/PMWR/CN13/RD4 91 AN23/CN39/RA6 82 RP20/PMRD/CN14/RD5 92 AN22/PMA17/CN40/RA7 83 C3INB/PMD14/CN15/RD6 93 PMD0/CN58/RE0 84 C3INA/SESSEND/PMD15/CN16/RD7 94 PMD1/CN59/RE1 85 VCAP 95 PMA16/CN81/RG14 86 ENVREG 96 CN79/RG12 87 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 97 CN80/RG13 88 VCMPST2/SESSVLD/PMD10/CN69/RF1 98 PMD2/CN60/RE2 89 PMD9/CN78/RG1 9
PIC24FJ256GB210 FAMILY Pin Diagram – Top View (121-Pin BGA)(1) Note 1: Legend: 1 2 3 4 5 6 7 8 9 10 A RE4 RE3 RG13 RE0 RG0 RF1 ENVREG N/C RD12 RD2 RD1 B N/C RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 C RE6 VDD RG12 RG14 RA6 N/C RD7 RD4 VDD RC13 RD11 D RC1 RE7 RE5 VSS VSS N/C RD6 RD13 RD0 n/c RD10 E RC4 RC3 RG6 RC2 VDD RG1 N/C RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS n/c N/C VDD OSCI/ RC12 VSS OSCO/ RC15 G RE8 RE9 RA0 N/C
PIC24FJ256GB210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Pin Function Pin Function A1 PMD4/CN62/RE4 E5 VDD A2 PMD3/CN61/RE3 E6 PMD9/CN78/RG1 A3 CN80/RG13 E7 N/C A4 PMD0/CN58/RE0 E8 SDA1/RPI35/PMBE1/CN44/RA15 A5 PMD8/CN77/RG0 E9 DMLN/RTCC/RP2/CN53/RD8 A6 VCMPST2/SESSVLD/PMD10/CN69/RF1 E10 DPLN/RP4/PMACK2/CN54/RD9 A7 ENVREG E11 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 A8 N/C F1 MCLR A9 RPI42/PMD12/CN57/RD12 F2 AN19/C2IND/RP19/PMA3/PMA21(2
PIC24FJ256GB210 FAMILY TABLE 3: COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES (CONTINUED) Pin Function Pin Function J9 N/C L1 PGEC2/AN6/RP6/CN24/RB6 J10 RP15/CN74/RF8 L2 VREF-(1)/PMA7/CN41/RA9 J11 D-/CN84/RG3 L3 AVSS K1 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 L4 AN9/RP9/CN27/RB9 K2 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 L5 AN10/CVREF/PMA13/CN28/RB10 K3 VREF+(1)/PMA6/CN42/RA10 L6 RP31/CN76/RF13 K4 AN8/RP8/CN26/RB8 L7 AN13/PMA10/CTEDG1/CN31/RB13 K5 N/C L8 AN15/REFO/RP29/PMA0
PIC24FJ256GB210 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 31 3.0 CPU ....................................................................................................
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PIC24FJ256GB210 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ128GB206 • PIC24FJ256GB206 • PIC24FJ128GB210 • PIC24FJ256GB210 The PIC24FJ256GB210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a large data RAM, up to 96 Kbytes. The PIC24FJ256GB210 family allows the CPU to fetch data directly from an external memory device using the EPMP module. 1.1 1.1.
PIC24FJ256GB210 FAMILY 1.2 USB On-The-Go The USB On-The-Go (USB OTG) module provides on-chip functionality as a target device, compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB enabled applications on a microcontroller platform.
PIC24FJ256GB210 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB210 FAMILY: 64-PIN Features PIC24FJ128GB206 Operating Frequency PIC24FJ256GB206 DC – 32 MHz Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) 128K 256K 44,032 87,552 96K Interrupt Sources (soft vectors/NMI traps) 65 (61/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 52 Remappable Pins 29 (28 I/O, 1 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Cap
PIC24FJ256GB210 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB210 FAMILY: 100-PIN DEVICES Features PIC24FJ128GB210 Operating Frequency PIC24FJ256GB210 DC – 32 MHz Program Memory (bytes) 128K Program Memory (instructions) 256K 44,032 Data Memory (bytes) 87,552 96K Interrupt Sources (soft vectors/NMI traps) 65 (61/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 84 Remappable Pins 44 (32 I/O, 12 input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers
PIC24FJ256GB210 FAMILY FIGURE 1-1: PIC24FJ256GB210 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (12 I/O) 16 16 8 Data Latch EDS and Table Data Access Control Block Data RAM Up to 0x7FFF PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch Program Memory/ Extended Data Space PORTC(1) (8 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTD(1) (16 I/O
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer AN0 16 25 K2 I ANA AN1 15 24 K1 I ANA AN2 14 23 J2 I ANA AN3 13 22 J1 I ANA AN4 12 21 H2 I ANA AN5 11 20 H1 I ANA AN6 17 26 L1 I ANA AN7 18 27 J3 I ANA AN8 21 32 K4 I ANA AN9 22 33 L4 I ANA AN10 23 34 L5 I ANA Function Description AN11 24 35 J5 I ANA AN12 27 41 J7 I ANA AN13 28
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 121-Pin BGA I/O Input Buffer 74 B11 I ST 73 C10 I ST 25 K2 I ST 64-Pin TQFP/QFN 100-Pin TQFP CN0 48 CN1 47 CN2 16 CN3 15 24 K1 I ST CN4 14 23 J2 I ST CN5 13 22 J1 I ST CN6 12 21 H2 I ST CN7 11 20 H1 I ST CN8 4 10 E3 I ST CN9 5 11 F4 I ST CN10 6 12 F2 I ST CN11 8 14 F3 I ST CN12 30 44 L8 I ST CN13 52 81 C8 I ST
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer CN40 — 92 B5 I ST CN41 — 28 L2 I ST CN42 — 29 K3 I ST CN43 — 66 E11 I ST CN44 — 67 E8 I ST CN45 — 6 D1 I ST CN46 — 7 E4 I ST CN47 — 8 E2 I ST CN48 — 9 E1 I ST CN49 46 72 D9 I ST CN50 49 76 A11 I ST CN51 50 77 A10 I ST CN52 51 78 B9 I ST CN53 42 68 E9 I ST CN54 4
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer CN81 — 95 C4 I ST CN82 — 1 B2 I ST CN83 37 57 H10 I ST CN84 36 56 J11 I ST CTEDG1 28 42 L7 I ANA CTEDG2 27 41 J7 I ANA CTPLS 29 43 K7 O — Function Description Interrupt-on-Change Inputs. CTMU External Edge Input 1. CTMU External Edge Input 2. CTMU Pulse Output.
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer PMA0 30 44 L8 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 43 K7 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes).
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer PMD0 60 93 A4 I/O ST/TTL PMD1 61 94 B4 I/O ST/TTL PMD2 62 98 B3 I/O ST/TTL Function PMD3 63 99 A2 I/O ST/TTL PMD4 64 100 A1 I/O ST/TTL PMD5 1 3 D3 I/O ST/TTL PMD6 2 4 C1 I/O ST/TTL PMD7 3 5 D2 I/O ST/TTL PMD8 — 90 A5 I/O ST/TTL Description Parallel Master Port Data bits<15:0>.
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RB0 16 25 K2 I/O ST RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST Function RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RD0 46 72 D9 I/O ST RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O Input Buffer RG0 — 90 A5 I/O ST RG1 — 89 E6 I/O ST RG2 37 57 H10 I/O ST RG3 36 56 J11 I/O ST RG6 4 10 E3 I/O ST Function RG7 5 11 F4 I/O ST RG8 6 12 F2 I/O ST RG9 8 14 F3 I/O ST RG12 — 96 C3 I/O ST RG13 — 97 A3 I/O ST RG14 — 95 C4 I/O ST RG15 — 1 B2 I/O ST RP0 16 25 K2 I/O ST RP1
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function Input Buffer 64-Pin TQFP/QFN 100-Pin TQFP 121-Pin BGA I/O RP20 53 82 B8 I/O ST RP21 4 10 E3 I/O ST RP22 51 78 B9 I/O ST RP23 50 77 A10 I/O ST RP24 49 76 A11 I/O ST RP25 52 81 C8 I/O ST RP26 5 11 F4 I/O ST ST RP27 8 14 F3 I/O RP28 12 21 H2 I/O ST RP29 30 44 L8 I/O ST RP30 — 52 K11 I/O ST RP31 — 39 L6 I/O ST RPI32 — 40 K6
PIC24FJ256GB210 FAMILY TABLE 1-3: PIC24FJ256GB210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 121-Pin BGA I/O Input Buffer 38 J6 I ST JTAG Test Clock Input. 60 G11 I ST JTAG Test Data Input. 61 G9 O — JTAG Test Data Output. 64-Pin TQFP/QFN 100-Pin TQFP TCK 27 TDI 28 TDO 24 Description TMS 23 17 G3 I ST JTAG Test Mode Select Input. USBID 33 51 K10 I ST USB OTG ID (OTG mode only).
PIC24FJ256GB210 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG and VCAP pins (PIC24FJ devices only) (see Section 2.
PIC24FJ256GB210 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FJ256GB210 FAMILY 2.4 Note: Voltage Regulator Pins (ENVREG and VCAP) FIGURE 2-3: This section applies only to PIC24FJ devices with an on-chip voltage regulator. 10 The on-chip voltage regulator enable pin (ENVREG) must always be connected directly to a supply voltage. When the regulator is enabled, a low-ESR (<5Ω) capacitor is required on the VCAP pin to stabilize the voltage regulator output voltage.
PIC24FJ256GB210 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FJ256GB210 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins. Depending on the particular device, this is done by clearing all bit in the ANSx registers. All PIC24FJ devices will have several ANSx registers (one for each port). Refer to (Section 10.0 “I/O Ports”) for more specific information.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 36 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 44. “CPU with Extended Data Space (EDS)” (DS39732). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 Data RAM Up to 0x7FFF PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 Address Latch 23 16 RAGU WAGU Address Latch EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 16 Literal Data Program Memory/
PIC24FJ256GB210 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 9 Program Counter Table Memory Page Address Register 0 Data Space Read Page Register DSRPAG 8 0 Data Space Write Page Register DSWPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL RA N OV Z C 2 1 0 15 Stack Pointer Limit Value Register
PIC24FJ256GB210 FAMILY 3.
PIC24FJ256GB210 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: C = Clearable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 =
PIC24FJ256GB210 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24FJ256GB210 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows direct access of program memory from the data space during code execution. 4.1 Program Memory Space The program address memory space of the PIC24FJ256GB210 family devices is 4M instructions.
PIC24FJ256GB210 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In PIC24FJ256GB210 family devices, the top four words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration register. The addresses of the Flash Configuration Word for devices in the PIC24FJ256GB210 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1.
PIC24FJ256GB210 FAMILY 4.2 Data Memory Space Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 45. “Data Memory with Extended Data Space (EDS)” (DS39733). The information in this data sheet supersedes the information in the FRM. The PIC24F core has a 16-bit wide data memory space, addressable as a single linear range.
PIC24FJ256GB210 FAMILY 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.
PIC24FJ256GB210 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® MCUs and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory.
File Name CPU CORE REGISTERS MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 2010 Microchip Technology I
2010 Microchip Technology Inc.
INTERRUPT CONTROLLER REGISTER MAP 2010 Microchip Technology Inc.
2010 Microchip Technology Inc.
INPUT CAPTURE REGISTER MAP 2010 Microchip Technology Inc.
2010 Microchip Technology Inc.
OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets OC8CON1 01D6 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC8RS 01DA Output Compare 8 Seconda
2010 Microchip Technology Inc.
File Name SPI REGISTER MAPS Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000 DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000 — — — — — — — — — — SPIFE SPIBEN 0000 SPIRBF 0000 Addr Bit 15 Bit 14 Bit 13 Bit 12 SPI1STAT 0240 SPIEN — SPISIDL SPI1CON1 0242 — — — SPI1CON2 0244 FRMEN SPIF
2010 Microchip Technology Inc.
File Name PORTF REGISTER MAP Addr Bit 15 Bit 14 Bit 13(1) Bit 12(1) Bit 11 Bit 10 Bit 9 Bit 8(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2(1) Bit 1 Bit 0 All Resets TRISF 02E8 — — TRISF13 TRISF12 — — — TRISF8 TRISF7 — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31BF PORTF 02EA — — RF13 RF12 — — — RF8 RF7 — RF5 RF4 RF3 RF2 RF1 RF0 xxxx LATF 02EC — — LATF13 LATF12 — — — LATF8 LATF7 — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx ODCF 02EE — —
2010 Microchip Technology Inc.
File Name ADC REGISTER MAP (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000 AD1CON2 0322 VCFG2 VCFG1 VCFG0 r — CSCNA — — BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 AD1CON3 0324 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS
2010 Microchip Technology Inc.
File Name USB OTG REGISTER MAP (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets U1EP10 04BE — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 U1EP11 04C0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 U1EP12 04C2 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 U1EP13 04C4 — — — — — — — — — —
2010 Microchip Technology Inc.
File Name COMPARATORS REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 C3EVT C2EVT C1EVT CMSTAT 0630 CMIDL — — — CVRCON 0632 — — — — — CM1CON 0634 CON COE CPOL — — — CEVT CM2CON 0636 CON COE CPOL — — — CM3CON 0638 CON COE CPOL — — — Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 — — — — — C3OUT C2OUT C1OUT CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 COUT EVPOL1 EVPOL0 — CREF — —
2010 Microchip Technology Inc.
File Name PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06C0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 RPOR1 06C2 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 RPOR2 06C4 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) — — RP
2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) pages, each having 32 Kbytes of data. Mapping of the EDS page into the EDS window is done by using the Data Space Read register (DSRPAG<9:0>) for read operations and Data Space Write register (DSWPAG<8:0>) for write operations. Figure 4-4 displays the entire EDS space. The enhancement of the data space in PIC24FJ256GB210 family devices has been accomplished by a new technique, called the Extended Data Space (EDS).
PIC24FJ256GB210 FAMILY 4.2.5.1 Data Read from EDS Space In order to read the data from the EDS space, first, an Address Pointer is set up by loading the required EDS page number into the DSRPAG register and assigning the offset address to one of the W registers. Once the above assignment is done, the EDS window is enabled FIGURE 4-5: by setting bit 15 of the working register, assigned with the offset address; then, the contents of the pointed EDS location can be read.
PIC24FJ256GB210 FAMILY 4.2.5.2 Data Write into EDS Space In order to write data to EDS space, such as in EDS reads, an Address Pointer is set up by loading the required EDS page number into the DSWPAG register and assigning the offset address to one of the W registers. Once the above assignment is done, then the FIGURE 4-6: EDS window is enabled by setting bit 15 of the working register, assigned with the offset address, and the accessed location can be written.
PIC24FJ256GB210 FAMILY The page registers (DSRPAG/DSWPAG) do not update automatically while crossing a page boundary when the rollover happens, from 0xFFFF to 0x8000. While developing code in assembly, care must be taken to update the page registers when an Address Pointer crosses the page boundary. The ‘C’ compiler keeps track of the addressing and increments or decrements the page registers accordingly while accessing contiguous data memory locations.
PIC24FJ256GB210 FAMILY 4.2.6 4.3 SOFTWARE STACK Apart from its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer (SSP). The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-7.
PIC24FJ256GB210 FAMILY TABLE 4-35: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 DSRPAG<7:0>(2) Data EA<1
PIC24FJ256GB210 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
PIC24FJ256GB210 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING EDS The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs when the MSb of EA is ‘1’ and the DSRPAG<9> is also ‘1’.
PIC24FJ256GB210 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> = 10 and EA<15> = 1 Program Space DSRPAG 202h 23 15 Data Space 0 000000h 0000h Data EA<14:0> 010000h 017FFEh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window FFFFh 7FFFFEh FIGURE 4-11: ...while the lower 15 bits of the EA specify an exact address within the EDS area.
PIC24FJ256GB210 FAMILY EXAMPLE 4-3: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0202 , w0 mov w0 , DSRPAG ;page 0x202, consisting lower words, is selected for read mov #0x000A , w1 ;select the location (0x0A) to be read bset w1 , #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++] , w2 ;read Low byte mov.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 78 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 5.0 Note: FLASH PROGRAM MEMORY microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 4. “Program Memory” (DS39715). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.
PIC24FJ256GB210 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/S-0, HC(1) R/W-0(1) R-0, HSC(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: S = Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is
PIC24FJ256GB210 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON<3:0>) to ‘0010’ to configure for block erase.
PIC24FJ256GB210 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVM
PIC24FJ256GB210 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes (MSB) of the Flash address. The TBLWTL and TBLWTH instructions write the desired data into the EXAMPLE 5-5: write latches and specify the lower 16 bits of the program memory address to write to.
PIC24FJ256GB210 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 7. “Reset” (DS39712). The information in this data sheet supersedes the information in the FRM. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24FJ256GB210 FAMILY REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) R/W-0, HS R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS R/W-0 TRAPR IOPUWR — — — — CM VREGS(3) bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x =
PIC24FJ256GB210 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 6-1: bit 2 IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred Note that BOR is also set after a Power-on Reset.
PIC24FJ256GB210 FAMILY 6.1 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers.
PIC24FJ256GB210 FAMILY TABLE 6-3: Reset Type POR(7) BOR RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Clock Source EC ECPLL XT, HS, SOSC XTPLL, HSPLL FRC, FRCDIV FRCPLL LPRC EC ECPLL XT, HS, SOSC XTPLL, HSPLL FRC, FRCDIV FRCPLL LPRC SYSRST Delay System Clock Delay Notes TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + T
PIC24FJ256GB210 FAMILY 6.3.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: 6.3.
PIC24FJ256GB210 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The information in this data sheet supersedes the information in the FRM. The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU.
PIC24FJ256GB210 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap V
PIC24FJ256GB210 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source ADC1 Conversion Done Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable Priority 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0
PIC24FJ256GB210 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable Priority Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0> UART1 Error 65 000096h 000196h IFS4<1>
PIC24FJ256GB210 FAMILY The CORCON register contains the IPL3 bit, which, together with IPL<2:0>, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. a generic ISR is used for multiple vectors (such as when ISR remapping is used in bootloader applications) or to check if another interrupt is pending while in an ISR.
PIC24FJ256GB210 FAMILY REGISTER 7-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC r-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: r = Reserved bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 =
PIC24FJ256GB210 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interr
PIC24FJ256GB210 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector
PIC24FJ256GB210 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set
PIC24FJ256GB210 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 U2TXIF U2RXIF INT
PIC24FJ256GB210 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occur
PIC24FJ256GB210 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5
PIC24FJ256GB210 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 R/W-0, HS R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Re
PIC24FJ256GB210 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: C
PIC24FJ256GB210 FAMILY REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — IC9IF OC9IF SPI3IF SPF3IF U4TXIF U4RXIF bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 U4ERIF USB1IF MI2C3IF SI2C3IF U3TXIF U3RXIF U3ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ =
PIC24FJ256GB210 FAMILY REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 (CONTINUED) bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE
PIC24FJ256GB210 FAMILY REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bi
PIC24FJ256GB210 FAMILY REGISTER 7-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 Unimplemented: Read as ‘0’ bit 7 IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not e
PIC24FJ256GB210 FAMILY REGISTER 7-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Mas
PIC24FJ256GB210 FAMILY REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 — R/W-0 INT4IE (1) R/W-0 (1) INT3IE U-0 U-0 R/W-0 R/W-0 U-0 — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enabl
PIC24FJ256GB210 FAMILY REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt reques
PIC24FJ256GB210 FAMILY REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC9IE OC9IE SPI3IE SPF3IE U4TXIE U4RXIE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIE USB1IE MI2C3IE SI2C3IE U3TXIE U3RXIE U3ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit
PIC24FJ256GB210 FAMILY REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 (CONTINUED) bit 1 U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ REGISTER 7-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT
PIC24FJ256GB210 FAMILY REGISTER 7-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interru
PIC24FJ256GB210 FAMILY REGISTER 7-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ256GB210 FAMILY REGISTER 7-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Inte
PIC24FJ256GB210 FAMILY REGISTER 7-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ256GB210 FAMILY REGISTER 7-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input C
PIC24FJ256GB210 FAMILY REGISTER 7-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interru
PIC24FJ256GB210 FAMILY REGISTER 7-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ256GB210 FAMILY REGISTER 7-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Pri
PIC24FJ256GB210 FAMILY REGISTER 7-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capt
PIC24FJ256GB210 FAMILY REGISTER 7-27: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12
PIC24FJ256GB210 FAMILY REGISTER 7-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PMPIP2 PMPIP1 PMPIP0 — OC8IP2 OC8IP1 OC8IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrup
PIC24FJ256GB210 FAMILY REGISTER 7-29: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 E
PIC24FJ256GB210 FAMILY REGISTER 7-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4
PIC24FJ256GB210 FAMILY REGISTER 7-31: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority
PIC24FJ256GB210 FAMILY REGISTER 7-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CR
PIC24FJ256GB210 FAMILY REGISTER 7-33: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits 111 = I
PIC24FJ256GB210 FAMILY REGISTER 7-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP<2:0>
PIC24FJ256GB210 FAMILY REGISTER 7-36: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4ERIP2 U4ERIP1 U4ERIP0 — USB1IP2 USB1IP1 USB1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C3IP2 MI2C3IP1 MI2C3IP0 — SI2C3IP2 SI2C3IP1 SI2C3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read
PIC24FJ256GB210 FAMILY REGISTER 7-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI3IP2 SPI3IP1 SPI3IP0 — SPF3IP2 SPF3IP1 SPF3IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’
PIC24FJ256GB210 FAMILY REGISTER 7-38: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC9IP<2:0>: Input Capture Channel 9 Inter
PIC24FJ256GB210 FAMILY REGISTER 7-39: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0, HSC U-0 R/W-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = B
PIC24FJ256GB210 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS (INTCON1<15>) control bit if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 136 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 8.
PIC24FJ256GB210 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 24x PLL block, which generates the USB module clock, and a separate system clock through the 96 MHZ PLL. Refer to Section 8.
PIC24FJ256GB210 FAMILY 8.3 Control Registers The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The following four Special Function Registers control the operation of the oscillator: • • • • The OSCTUN register (Register 8-3) allows the user to fine tune the FRC oscillator over a range of approximately ±1.5%.
PIC24FJ256GB210 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FJ256GB210 FAMILY REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-0 DOZE2 DOZE1 R/W-0 DOZE0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-1 RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 r-0 U-0 U-0 U-0 U-0 CPDIV1 CPDIV0 PLLEN Reserved — — — — bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interr
PIC24FJ256GB210 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 TUN5 (1) R/W-0 (1) TUN4 R/W-0 (1) TUN3 R/W-0 TUN2 (1) R/W-0 TUN1 (1) R/W-0 TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscilla
PIC24FJ256GB210 FAMILY 8.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 8.4.1 2. ENABLING CLOCK SWITCHING 4.
PIC24FJ256GB210 FAMILY A recommended code sequence for a clock switch includes the following: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24FJ256GB210 FAMILY FIGURE 8-2: 96 MHz PLL BLOCK PLLDIV<2:0> Input from FRC (4 MHz or 8 MHz) 12 8 6 5 4 3 2 1 111 110 101 100 011 010 001 000 48 MHz Clock for USB Module 2 4 MHz 96 MHz PLL 3 32 MHz PLL Prescaler Input from POSC PLL Prescaler FNOSC<2:0> 8 4 2 1 11 10 01 00 PLL Output for System Clock CPDIV<1:0> 8.5.
PIC24FJ256GB210 FAMILY 8.5.2 USB CLOCK GENERATION In the USB-On-The-Go module in the PIC24FJ256GB210 family of devices, the primary oscillator with the PLL block can be used as a valid clock source for USB operation. The FRC oscillator (implemented with ±1.0% accuracy) can be combined with a PLL block, providing another option for a valid USB clock source. There is no provision to provide a separate external 48 MHz clock to the USB module.
PIC24FJ256GB210 FAMILY 8.5.3 CONSIDERATIONS FOR USB OPERATION When using the USB On-The-Go module in PIC24FJ256GB210 family devices, users must always observe these rules in configuring the system clock: • For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements. • The Primary Oscillator/PLL modes are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module.
PIC24FJ256GB210 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL(1) RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Refe
PIC24FJ256GB210 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 10. “Power-Saving Features” (DS39698). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY 9.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FJ256GB210 FAMILY 10.0 Note: I/O PORTS When a peripheral is enabled and it is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but it is not actively driving a pin, that pin may be driven by a port. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ256GB210 FAMILY 10.1.1 10.2 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. 10.1.2 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either a digital or open-drain output.
PIC24FJ256GB210 FAMILY REGISTER 10-1: ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 U-0 — — — — — ANSA10 ANSA9 — bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSA7 ANSA6 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 ANSA<10:9>: Analog Function Selection bits 1 = Pin i
PIC24FJ256GB210 FAMILY REGISTER 10-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknow
PIC24FJ256GB210 FAMILY REGISTER 10-4: ANSD: PORTD ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ANSD7 ANSD6 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 ANSD<7:6>: Analog Function Selection bits 1 = Pin is configured in Ana
PIC24FJ256GB210 FAMILY REGISTER 10-6: ANSF: PORTF ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 — — — — — — — ANSF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 ANSF0: Analog Function Selection bits 1 = Pin is configured in Analog mode; I/
PIC24FJ256GB210 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GB210 family of devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature is capable of detecting input Change-of-States, even in Sleep mode, when the clocks are disabled.
PIC24FJ256GB210 FAMILY 10.4 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option.
PIC24FJ256GB210 FAMILY TABLE 10-3: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name Register Function Mapping Bits External Interrupt 1 INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> External Interrupt 3 INT3 RPINR1 INT3R<5:0> External Interrupt 4 Input Name INT4 RPINR2 INT4R<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Input Capture 3 IC3 RPINR8 IC3R<5:0> Input Capture 4 IC4 RPINR8 IC4R<5:0> Input C
PIC24FJ256GB210 FAMILY 10.4.3.2 Output Mapping corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-4). In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
PIC24FJ256GB210 FAMILY 10.4.3.3 Mapping Limitations 10.4.4.1 The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention, caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lockouts.
PIC24FJ256GB210 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state.
PIC24FJ256GB210 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ256GB210 family of devices implements a total of 37 registers for remappable peripheral configuration: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 10.4.4.1 “Control Register Lock” for a specific command sequence.
PIC24FJ256GB210 FAMILY REGISTER 10-10: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R<5:0>: Assign Ex
PIC24FJ256GB210 FAMILY REGISTER 10-12: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ256GB210 FAMILY REGISTER 10-14: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ256GB210 FAMILY REGISTER 10-16: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0
PIC24FJ256GB210 FAMILY REGISTER 10-18: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC9R<5:0>: Assign Input
PIC24FJ256GB210 FAMILY REGISTER 10-20: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimple
PIC24FJ256GB210 FAMILY REGISTER 10-22: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GB210 FAMILY REGISTER 10-24: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GB210 FAMILY REGISTER 10-26: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimple
PIC24FJ256GB210 FAMILY REGISTER 10-28: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Sl
PIC24FJ256GB210 FAMILY REGISTER 10-29: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ256GB210 FAMILY REGISTER 10-31: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimpleme
PIC24FJ256GB210 FAMILY REGISTER 10-33: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ256GB210 FAMILY REGISTER 10-35: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ256GB210 FAMILY REGISTER 10-37: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ256GB210 FAMILY REGISTER 10-39: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GB210 FAMILY REGISTER 10-41: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GB210 FAMILY REGISTER 10-43: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 182 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 11.0 Note: TIMER1 Figure 11-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The information in this data sheet supersedes the information in the FRM. To configure Timer1 for operation: 1. 2. 3. 4.
PIC24FJ256GB210 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Re
PIC24FJ256GB210 FAMILY 12.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE(2) TGATE TCS(2) Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) ADC Event Trigger(3) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter
PIC24FJ256GB210 FAMILY FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK (T4CK) TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS(1) TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TMR2 (TMR4) TGATE(1) Sync Comparator PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
PIC24FJ256GB210 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-b
PIC24FJ256GB210 FAMILY REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 — R/W-0 R/W-0 (1) R/W-0 (1) TGATE TCKPS1 U-0 (1) TCKPS0 — U-0 — R/W-0 (1,2) TCS bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Time
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 190 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 13.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 13.1 13.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 34. “Input Capture with Dedicated Timer” (DS39722). The information in this data sheet supersedes the information in the FRM. Devices in the PIC24FJ256GB210 family comprise nine independent input capture modules.
PIC24FJ256GB210 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs and the even module (ICy) provides the Most Significant 16 bits.
PIC24FJ256GB210 FAMILY REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FJ256GB210 FAMILY REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0 HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unim
PIC24FJ256GB210 FAMILY 14.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 35. “Output Compare with Dedicated Timer” (DS39723). The information in this data sheet supersedes the information in the FRM. Devices in the PIC24FJ256GB210 family feature all of the 9 independent output compare modules.
PIC24FJ256GB210 FAMILY FIGURE 14-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxCON2 OCxR and DCB<1:0> OCx Pin(1) Match Event Clock Select OC Clock Sources Increment Comparator OC Output and Fault Logic OCxTMR Reset Match Event Trigger and Sync Sources Trigger and Sync Logic Comparator Match Event OCFA/OCFB(2) OCxRS Reset OCx Interrupt Note 1: The OCx outputs must be
PIC24FJ256GB210 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. 2. 3. 4. 5. 6. Set the OC32 bits for both registers (OCyCON2<8> and OCxCON2<8>). Enable the even numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2) so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCy. Force the output pin for OCx to the output state by clearing the OCTRIS bit.
PIC24FJ256GB210 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT<2:0> OCFLT<2:0> DCB<1:0> OCxCON2 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxR and DCB<1:0> Rollover/Reset OCxR and DCB<1:0> Buffers OCx Pin(1) Clock Select OC Clock Sources Increment Comparator OCxTMR Reset Trigger and Sync Logic Trigger and Sync Sources Match Event Comparator Match Event OC Output and Rollover Fault Logic OCFA/OCFB(2) Mat
PIC24FJ256GB210 FAMILY 14.3.2 PWM DUTY CYCLE • If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). • If OCxRS is greater than PRy, the pin will remain high (100% duty cycle). The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i.e., the period is complete).
PIC24FJ256GB210 FAMILY REGISTER 14-1: U-0 OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 — R/W-0 — R/W-0 OCSIDL OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 R/W-0 ENFLT2 (2) R/W-0 ENFLT1(2) bit 15 bit 8 R/W-0 R/W-0, HSC (2) ENFLT0 OCFLT2 (2) R/W-0, HSC OCFLT1 R/W-0, HSC (2) (2) OCFLT0 R/W-0 TRIGMODE R/W-0 (1) OCM2 R/W-0 OCM1 (1) R/W-0 OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Val
PIC24FJ256GB210 FAMILY REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx(2) 110 = Edge-Aligned PWM Mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize the OCx pin low, the toggle OCx state is continuously on alterna
PIC24FJ256GB210 FAMILY REGISTER 14-2: R/W-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 FLTMD FLTOUT R/W-0 R/W-0 FLTTRIEN OCINV U-0 R/W-0 DCB1 — R/W-0 (3) DCB0 R/W-0 (3) OC32 bit 15 bit 8 R/W-0 R/W-0 HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0
PIC24FJ256GB210 FAMILY REGISTER 14-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 10
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 204 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 15.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY To set up the SPI module for the Standard Master mode of operation: To set up the SPI module for the Standard Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ256GB210 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1.
PIC24FJ256GB210 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN(1) — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0, HSC R/C-0, HS R-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’
PIC24FJ256GB210 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FJ256GB210 FAMILY REGISTER 15-2: U-0 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 — — U-0 — R/W-0 DISSCK (1) R/W-0 (2) DISSDO R/W-0 R/W-0 R/W-0 MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(4) CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’
PIC24FJ256GB210 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 . . . 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.
PIC24FJ256GB210 FAMILY REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD SPIFPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled 0 = Framed SPIx support is disable
PIC24FJ256GB210 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) Processor 1 (SPI Master) Processor 2 (SPI Slave) SDOx SDIx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB)(2) SDIx Shift Register (SPIxSR) SDOx LSb MSb MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF)(2) Shift Register (SPIxSR)(2) LSb Serial Transmit Buffer (SPIxTXB)(2) SCKx Serial Clock SCKx SPIx Buffer (SPIxBUF)(2) SSx(1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 MSTEN (
PIC24FJ256GB210 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM Processor 2 PIC24F (SPI Master, Frame Master) SDIx SDOx SDOx SDIx SCKx SSx FIGURE 15-6: Serial Clock Frame Sync Pulse SCKx SSx SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F SPI Master, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 15-7: Processor 2 Serial Clock Frame Sync Pulse SCKx SSx SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM Processor 2 PIC24F (SPI Slave, Frame Master) SDOx SDIx SDIx SDOx SCKx
PIC24FJ256GB210 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FSCK = Note 1: TABLE 15-1: FCY Primary Prescaler x Secondary Prescaler Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 216 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT™ (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS39702). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS39975A-page 218 2010 Microchip Technol
PIC24FJ256GB210 FAMILY 16.2 Setting Baud Rate When Operating as a Bus Master 16.3 The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00100000’, the slave module will detect both addresses, ‘0000000’ and ‘0100000’.
PIC24FJ256GB210 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B
PIC24FJ256GB210 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24FJ256GB210 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
PIC24FJ256GB210 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
PIC24FJ256GB210 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 A
PIC24FJ256GB210 FAMILY 17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated, 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 shows the formula for computation of the baud rate with BRGH = 1.
PIC24FJ256GB210 FAMILY 17.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write a data byte to the lower byte of UxTXREG word.
PIC24FJ256GB210 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
PIC24FJ256GB210 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard-Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Se
PIC24FJ256GB210 FAMILY REGISTER 17-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV (1) R/W-0 U-0 UTXISEL0 — R/W-0 HC R/W-0 R-0, HSC R-1, HSC UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n
PIC24FJ256GB210 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 232 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 18.0 Note: UNIVERSAL SERIAL BUS WITH ON-THE-GO SUPPORT (USB OTG) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 27. “USB On-The-Go (OTG)” (DS39721). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY FIGURE 18-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up 48 MHz USB Clock Host Pull-Down D+(1) Registers and Control Interface Transceiver VUSB Transceiver Power 3.
PIC24FJ256GB210 FAMILY 18.1 Hardware Configuration 18.1.1 DEVICE MODE 18.1.1.1 D+ Pull-up Resistor PIC24FJ256GB210 family devices have a built-in 1.5 k resistor on the D+ line that is available when the microcontroller is operating in Device mode. This is used to signal an external Host that the device is operating in Full-Speed Device mode. It is engaged by setting the USBEN bit (U1CON<0>). If the OTGEN bit (U1OTGCON<2>) is set, then the D+ pull-up is enabled through the DPPULUP bit (U1OTGCON<7>).
PIC24FJ256GB210 FAMILY FIGURE 18-5: DUAL POWER EXAMPLE 100 VBUS ~5V Attach Sense 3.3V controller is operating in Host mode. They are engaged by setting the HOSTEN bit (U1CON<3>). If the OTGEN bit (U1OTGCON<2>) is set, then these pull-downs are enabled by setting the DPPULDWN and DMPULDWN bits (U1OTGCON<5:4>). VBUS VDD 18.1.2.2 Low IQ Regulator In Host mode, as well as Host mode in On-The-Go operation, the “USB 2.0 OTG Specification” requires that the host application should supply power on VBUS.
PIC24FJ256GB210 FAMILY FIGURE 18-7: OTG INTERFACE EXAMPLE VDD PIC® MCU MCP1253 1 µF Micro A/B Connector 4.7 µF GND C+ VIN SELECT CVOUT SHND PGOOD VBUS Voltage Generation with External Devices When operating as a USB host, either as an A-device in an OTG configuration or as an embedded host, VBUS must be supplied to the attached device. PIC24FJ256GB210 family devices have an internal VBUS boost assist to help generate the required 5V VBUS from the available voltages on the board.
PIC24FJ256GB210 FAMILY EQUATION 18-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = 40 mA • VUSB • PZERO • PIN • LCABLE + IPULLUP 3.3V • 5m Legend: VUSB – Voltage applied to the VUSB pin in volts (3.0V to 3.6V). PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® microcontroller that are a value of ‘0’. PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE – Length (in meters) of the USB cable. The “USB 2.
PIC24FJ256GB210 FAMILY 18.2 USB Buffer Descriptors and the BDT Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. The BDT can be located in any available, 512-byte aligned block of data RAM. The BDT Pointer (U1BDTP1) contains the upper address byte of the BDT and sets the location of the BDT in RAM.
PIC24FJ256GB210 FAMILY BDs have a fixed relationship to a particular endpoint, depending on the buffering configuration. Table 18-2 provides the mapping of BDs to endpoints. This relationship also means that gaps may occur in the BDT if endpoints are not enabled contiguously. This, theoretically, means that the BDs for disabled endpoints could be used as buffer space. In practice, users should avoid using such spaces in the BDT unless a method of validating BD addresses is implemented. 18.2.
PIC24FJ256GB210 FAMILY REGISTER 18-1: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC UOWN DTS PID3 PID2 PID1 PID0 BC9 BC8 bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit
PIC24FJ256GB210 FAMILY REGISTER 18-2: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x r-0 r-0 R/W-x R/W-x R/W-x, HSC R/W-x, HSC UOWN DTS(1) Reserved Reserved DTSEN BSTALL BC9 BC8 bit 15 bit 8 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimpl
PIC24FJ256GB210 FAMILY 18.3 USB Interrupts level consists of USB error conditions, which are enabled and flagged in the U1EIR and U1EIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use the same interrupt vector. Interrupts may be used to trap routine events in a USB transaction.
PIC24FJ256GB210 FAMILY 18.3.1 CLEARING USB OTG INTERRUPTS Unlike device level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in FIGURE 18-10: software by writing a ‘1’ to their locations (i.e., performing a MOV type instruction). Writing a ‘0’ to a flag bit (i.e., a BCLR instruction) has no effect.
PIC24FJ256GB210 FAMILY 18.4.2 1. 2. 3. 4. Attach to a USB host and enumerate as described in Chapter 9 of the “USB 2.0 Specification”. Create a data buffer and populate it with the data to send to the host. In the appropriate (even or odd) TX BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer.
PIC24FJ256GB210 FAMILY 18.5.2 1. 2. 3. 4. 5. 6. 7. COMPLETE A CONTROL TRANSACTION TO A CONNECTED DEVICE Follow the procedure described in Section 18.5.1 “Enable Host Mode and Discover a Connected Device” to discover a device. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the EPCONDIS, EPTXEN and EPHSHK bits). Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the “USB 2.
PIC24FJ256GB210 FAMILY 18.5.3 1. 2. 3. 4. 5. 6. 7. SEND A FULL-SPEED BULK DATA TRANSFER TO A TARGET DEVICE Follow the procedure described in Section 18.5.1 “Enable Host Mode and Discover a Connected Device” and Section 18.5.2 “Complete a Control Transaction to a Connected Device” to discover and configure a device. To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is a low-speed device, also set the LSPD (U1EP0<7>) bit.
PIC24FJ256GB210 FAMILY 18.6.2 HOST NEGOTIATION PROTOCOL (HNP) In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral. Any OTG DRD must support Host Negotiation Protocol (HNP). HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to follow HNP. Refer to the “On-The-Go Supplement” to the “USB 2.0 Specification” for more information regarding HNP. HNP may only be initiated at full speed.
PIC24FJ256GB210 FAMILY 18.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: • • • • USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 18-1 and Register 18-2, are shown separately in Section 18.2 “USB Buffer Descriptors and the BDT”.
PIC24FJ256GB210 FAMILY 18.7.
PIC24FJ256GB210 FAMILY REGISTER 18-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 DPPULUP DMPULUP R/W-0 R/W-0 DPPULDWN(1) DMPULDWN(1) R/W-0 R/W-0 VBUSON(1) OTGEN(1) R/W-0 R/W-0 VBUSCHG(1) VBUSDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’
PIC24FJ256GB210 FAMILY REGISTER 18-5: U1PWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0, HS U-0 U-0 UACTPND — — R/W-0 U-0 U-0 R/W-0, HC R/W-0 USLPGRD — — USUSPND USBPWR bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented:
PIC24FJ256GB210 FAMILY REGISTER 18-6: U1STAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0, HSC ENDPT3 R-0, HSC R-0, HSC ENDPT2 ENDPT1 R-0, HSC ENDPT0 R-0, HSC DIR R-0, HSC (1) PPBI U-0 U-0 — — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT
PIC24FJ256GB210 FAMILY REGISTER 18-7: U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — SE0 PKTDIS — HOSTEN RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as
PIC24FJ256GB210 FAMILY REGISTER 18-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY USBRST HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Un
PIC24FJ256GB210 FAMILY REGISTER 18-9: U1ADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 (1) LSPDEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB
PIC24FJ256GB210 FAMILY REGISTER 18-11: U-0 — bit 15 U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CNT<7:0>: Star
PIC24FJ256GB210 FAMILY REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 — — UVCMPSEL PUVBUS EXTI2CEN R/W-0 R/W-0 UVBUSDIS(1) UVCMPDIS(1) R/W-0 UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 UVCMPSEL: VBUS Co
PIC24FJ256GB210 FAMILY 18.7.
PIC24FJ256GB210 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interru
PIC24FJ256GB210 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FJ256GB210 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FJ256GB210 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 STALLIE ATTACHIE (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESUMEIE IDLEIE TRNIE SOFIE UERRIE R/W-0 URSTIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as
PIC24FJ256GB210 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS BTSEF — DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF EOFEF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
PIC24FJ256GB210 FAMILY REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE — DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE EOFEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enab
PIC24FJ256GB210 FAMILY 18.7.
PIC24FJ256GB210 FAMILY 18.7.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 268 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 19.0 ENHANCED PARALLEL MASTER PORT (EPMP) Note: Key features of the EPMP module are: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 42. “Enhanced Parallel Master Port (EPMP)” (DS39730). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY TABLE 19-2: PARALLEL MASTER PORT PIN DESCRIPTION Pin Name Type PMA<22:16>(1) O Address Bus Bits<22-16> O Address Bus Bit<15> O Chip Select 2 (alternate location) I/O Data Bus Bit<15> when port size is 16 bits and address is multiplexed O Address Bus Bit<14> O Chip Select 1 (alternate location) I/O Data Bus Bit<14> when port size is 16-bit and address is multiplexed O Address Bus Bits<13-8> I/O Data Bus Bits<13-8> when port size is 16 bits and address is multiplex
PIC24FJ256GB210 FAMILY REGISTER 19-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 PMPEN bit 15 U-0 — R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 U-0 — R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 CSF1 bit 7 R/W-0 CSF0 R/W-0 ALP R/W-0 ALMODE U-0 — R/W-0 BUSKEEP R/W-0 IRQM1 R/W-0 IRQM0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12-11 bit 10 bit 9-8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is c
PIC24FJ256GB210 FAMILY REGISTER 19-2: R-0, HSC BUSY PMCON2: EPMP CONTROL REGISTER 2 U-0 — R/C-0, HS ERROR R/C-0, HS TIMEOUT U-0 U-0 U-0 U-0 — — — — bit 15 R/W-0 RADDR23 bit 7 bit 8 R/W-0 RADDR22 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11-8 bit 7-0 Note 1: R/W-0 RADDR21 R/W-0 RADDR20 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set R/W-0 RADDR19 R/W-0 RADDR18 R/W-0 RADDR17 R/W-0 RADDR16 bit 0 HSC = Hardware Settable/Clearable bit U = Un
PIC24FJ256GB210 FAMILY REGISTER 19-3: R/W-0 PTWREN bit 15 U-0 — PMCON3: EPMP CONTROL REGISTER 3 R/W-0 PTRDEN R/W-0 PTBE1EN R/W-0 PTBE0EN U-0 — R/W-0 AWAITM1 R/W-0 AWAITM0 R/W-0 AWAITE bit 8 R/W-0 PTEN22(1) R/W-0 PTEN21(1) R/W-0 PTEN20(1) R/W-0 PTEN19(1) R/W-0 PTEN18(1) R/W-0 PTEN17(1) R/W-0 PTEN16(1) bit 0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-9 bit bit 8 bit 7 bit 6-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bi
PIC24FJ256GB210 FAMILY REGISTER 19-4: PMCON4: EPMP CONTROL REGISTER 4 R/W-0 PTEN15 bit 15 R/W-0 PTEN14 R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 8 R/W-0 PTEN7 bit 7 R/W-0 PTEN6 R/W-0 PTEN5 R/W-0 PTEN4 R/W-0 PTEN3 R/W-0 PTEN2 R/W-0 PTEN1 R/W-0 PTEN0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-3 bit 2-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PTEN15: PMA1
PIC24FJ256GB210 FAMILY REGISTER 19-5: PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSDIS CSP CSPTEN BEP — WRSP RDSP SM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ACKP PTSZ1 PTSZ0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CSDIS: Chip Select x Disable bit 1 = Disable the Chip Select x function
PIC24FJ256GB210 FAMILY REGISTER 19-6: PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) BASE23 BASE22 BASE21 BASE20 BASE19 BASE18 BASE17 BASE16 bit 15 bit 8 R/W(1) U-0 U-0 U-0 R/W(1) U-0 U-0 U-0 BASE15 — — — BASE11 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 BASE<23:15>: Chip Select x Base Address b
PIC24FJ256GB210 FAMILY REGISTER 19-7: PMCSxMD: CHIP SELECT x MODE REGISTER R/W-0 ACKM1 bit 15 R/W-0 ACKM0 R/W-0 DWAITB1 bit 7 R/W-0 DWAITB0 bit 13-8 bit 7-6 bit 5-2 U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15-14 U-0 — R/W-0 DWAITM3 W = Writable bit ‘1’ = Bit is set R/W-0 DWAITM2 R/W-0 DWAITM1 R/W-0 DWAITM0 R/W-0 DWAITE1 R/W-0 DWAITE0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ACKM<1:0>: Chip Select x Ackno
PIC24FJ256GB210 FAMILY REGISTER 19-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) R-0, HSC IBF bit 15 R/W-0 HS IBOV U-0 — U-0 — R-0, HSC IB3F R-0, HSC IB2F R-0, HSC IB1F R-0, HSC IB0F bit 8 R-1, HSC OBE bit 7 R/W-0 HS OBUF U-0 — U-0 — R-1, HSC OB3E R-1, HSC OB2E R-1, HSC OB1E R-1, HSC OB0E bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 Note 1: HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HSC = Hardwar
PIC24FJ256GB210 FAMILY REGISTER 19-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds c
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 280 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 20.
PIC24FJ256GB210 FAMILY 20.1 RTCC Module Registers TABLE 20-2: The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 20.1.1 To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through the corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 20-1).
PIC24FJ256GB210 FAMILY 20.1.
PIC24FJ256GB210 FAMILY REGISTER 20-1: bit 7-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment . . .
PIC24FJ256GB210 FAMILY REGISTER 20-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
PIC24FJ256GB210 FAMILY 20.1.
PIC24FJ256GB210 FAMILY REGISTER 20-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC R/W-x, HSC — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
PIC24FJ256GB210 FAMILY 20.1.
PIC24FJ256GB210 FAMILY REGISTER 20-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-
PIC24FJ256GB210 FAMILY 20.2 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register.
PIC24FJ256GB210 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when conf
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 292 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 21.0 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR Note: The 32-bit programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications.
PIC24FJ256GB210 FAMILY 21.1 21.1.1 User Interface 21.1.2 POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up of up the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN<4:0> bits (CRCCON2<4:0>). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation.
PIC24FJ256GB210 FAMILY 21.1.3 DATA SHIFT DIRECTION The LENDIAN bit (CRCCON1<3>) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction the data is shifted into the engine.
PIC24FJ256GB210 FAMILY REGISTER 21-1: CRCCON1: CRC CONTROL 1 REGISTER R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 R-0, HSC CRCFUL bit 8 R-1, HSC CRCMPT R/W-0 CRCISEL R/W-0, HC CRCGO R/W-0 U-0 U-0 U-0 LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is
PIC24FJ256GB210 FAMILY REGISTER 21-2: CRCCON2: CRC CONTROL 2 REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDT
PIC24FJ256GB210 FAMILY REGISTER 21-4: CRCXORH: CRC XOR HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X31 X30 X29 X28 X27 X26 X25 X24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X23 X22 X21 X20 X19 X18 X17 X16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X<31:16>: XOR of Polynomial Term xn Enable bits RE
PIC24FJ256GB210 FAMILY REGISTER 21-7: CRCWDATL: CRC SHIFT LOW REGISTER R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA15 SDATA14 SDATA13 SDATA12 SDATA11 SDATA10 SDATA9 SDATA8 bit 15 bit 8 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC SDATA7 SDATA6 SDATA5 SDATA4 SDATA3 SDATA2 SDATA1 SDATA0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 300 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 22.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). The information in this data sheet supersedes the information in the FRM. A block diagram of the A/D Converter is shown in Figure 22-1. To perform an A/D conversion: 1.
PIC24FJ256GB210 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD VR+ 16 VR- VREF- Comparator VINH AN0 VINL VRS/H VR+ DAC AN1 AN2 10-Bit SAR MUX A VINH Conversion Logic Data Formatting AD1BUF0: AD1BUF1F VINL AD1CON1 AN23 VBG MUX B AD1CON2 AD1CON3 AD1CHS ANCFG VINH AD1CSSL AD1CSSH VINL VBG/2 VBG/6 VCAP Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control DS39975A-page 302 2010 Microc
PIC24FJ256GB210 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0, HSC R-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D
PIC24FJ256GB210 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x =
PIC24FJ256GB210 FAMILY REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source
PIC24FJ256GB210 FAMILY REGISTER 22-4: R/W-0 AD1CHS: A/D INPUT SELECT REGISTER U-0 CH0NB — U-0 — R/W-0 CH0SB4 R/W-0 (1) CH0SB3 R/W-0 (1) R/W-0 (1) CH0SB2 CH0SB1 R/W-0 (1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4(1) CH0SA3(1) CH0SA2(1) CH0SA1(1) CH0SA0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH
PIC24FJ256GB210 FAMILY REGISTER 22-5: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — VBG6EN VBG2EN VBGEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2 VBG6EN: A/D Input VBG/6 Enable bit 1 =
PIC24FJ256GB210 FAMILY REGISTER 22-7: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CSSL27 CSSL26 CSSL25 CSSL24 bit 15 bit 8 R/W-0 CSSL23 R/W-0 (1) (1) CSSL22 R/W-0 CSSL21 (1) R/W-0 CSSL20 (1) R/W-0 CSSL19 (1) R/W-0 CSSL18 R/W-0 (1) (1) CSSL17 R/W-0 CSSL16(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is un
PIC24FJ256GB210 FAMILY FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC 250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS 5 k(Typical) RSS CHOLD = DAC Capacitance = 4.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 310 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 23.0 TRIPLE COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”. The triple comparator module provides three dual input comparators.
PIC24FJ256GB210 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN = 0, CREF = x, CCH<1:0> = xx COE VINVIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CEN = 1, CCH<1:0> = 00 Comparator CxINC > CxINA Compare CVREFM<1:0> = xx VIN+ CXINA CEN = 1, CCH<1:0> = 01 COE VIN- CXINB Cx CxOUT Pin VIN+ CXINA VBG/2 CXINA VIN+ CxOUT Pin COE CVREFM<1:0> = 00 Cx CxOUT Pin COE VIN- VBG Cx VIN+ CXINA CxOUT Pin Comparator VBG > CxINA Compare CVRE
PIC24FJ256GB210 FAMILY FIGURE 23-3: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN = 1, CCH<1:0> = 00 CEN = 1, CCH<1:0> = 01 CXINB CVREF CVREFM<1:0> = xx COE VIN- CXINC VIN+ Cx CVREF CxOUT Pin CXIND CVREF COE VBG Cx CVREF CxOUT Pin VBG/2 CVREF CxOUT Pin CVREFM<1:0> = 00 COE VINVIN+ CEN = 1, CCH<1:0> = 11 CVREFM<1:0> = 01 COE VIN- VBG/6 Cx VIN+ Cx Cx CxOUT Pin Comparator VBG > CVREF Compare
PIC24FJ256GB210 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0, HS R-0, HSC CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ =
PIC24FJ256GB210 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CXINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM<1:0> bits
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 316 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE 24.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 19. “Comparator Module” (DS39710). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0
PIC24FJ256GB210 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724). The information in this data sheet supersedes the information in the FRM.
PIC24FJ256GB210 FAMILY 25.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN (CTMUCON<12>) bit, the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected.
PIC24FJ256GB210 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HSC R/W-0, HSC EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit i
PIC24FJ256GB210 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin.
PIC24FJ256GB210 FAMILY 26.0 Note: SPECIAL FEATURES 26.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”. The information in this data sheet supersedes the information in the FRMs. In PIC24FJ256GB210 family devices, the configuration bytes are implemented as volatile memory.
PIC24FJ256GB210 FAMILY REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 reserved JTAGEN GCP GWRP DEBUG reserved ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS ALTVREF(1) FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit
PIC24FJ256GB210 FAMILY REGISTER 26-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Note 1: Unimplemented in 64-pin devices, maintain at
PIC24FJ256GB210 FAMILY REGISTER 26-2: CW2: FLASH CONFIGURATION WORD 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 IESO PLLDIV2 PLLDIV1 PLLDIV0 PLL96MHZ FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 r-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN IOL1WAY reserved reserved POSCMD1 POSCMD0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Un
PIC24FJ256GB210 FAMILY REGISTER 26-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
PIC24FJ256GB210 FAMILY REGISTER 26-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) bit 11-10 WUTSEL<1:0>: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use bit 9-8 SOSCSEL<1:0>: SOSC Selection Configuration bits 11 = Secondary oscillator is in Default (high drive strength) Oscillator mode 10 = Reserved; do not use 01 = Secondary oscillator is in Low-Power (low drive strength) Oscillator
PIC24FJ256GB210 FAMILY REGISTER 26-5: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-16 Unimplemented: Read as ‘1’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 01000001 = PIC24FJ256GB210 family bit
PIC24FJ256GB210 FAMILY 26.2 On-Chip Voltage Regulator All PIC24FJ256GB210 family devices power their core digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GB210 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin.
PIC24FJ256GB210 FAMILY 26.3 Watchdog Timer (WDT) For PIC24FJ256GB210 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit.
PIC24FJ256GB210 FAMILY 26.4 Program Verification and Code Protection PIC24FJ256GB210 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 26.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256GB210 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS).
PIC24FJ256GB210 FAMILY 26.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 334 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 27.
PIC24FJ256GB210 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC24FJ256GB210 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FJ256GB210 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24FJ256GB210 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FJ256GB210 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C,
PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 W
PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 No
PIC24FJ256GB210 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 346 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256GB210 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GB210 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FJ256GB210 FAMILY 29.1 DC Characteristics FIGURE 29-1: PIC24FJ256GB210 FAMILY VOLTAGE FREQUENCY GRAPH (INDUSTRIAL) 3.6V 3.6V Voltage (VDD) PIC24FJXXXDA1 2.2V VBOR 2.2V VBOR 32 MHz Frequency Note: TABLE 29-1: VCAP (nominal On-Chip Regulator output voltage) = 1.8V.
PIC24FJ256GB210 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Min Typ Max Units Conditions VBOR — 3.6 V Regulator enabled Regulator enabled Operating Voltage DC10 Supply Voltage VDD VCAP(2) — 1.8V — V DC12 VDR RAM Data Retention Voltage(1) 1.
PIC24FJ256GB210 FAMILY TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC20D 0.8 1.3 mA -40°C DC20E 0.8 1.3 mA +25°C DC20F 0.8 1.3 mA +85°C DC23D 3.0 4.8 mA -40°C DC23E 3.0 4.8 mA +25°C DC23F 3.0 4.8 mA +85°C DC24D 12.0 18 mA -40°C DC24E 12.
PIC24FJ256GB210 FAMILY TABLE 29-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE)(2) DC40D 170 320 A -40°C DC40E 170 320 A +25°C DC40F 220 380 A +85°C DC43D 0.6 1.2 mA -40°C DC43E 0.6 1.2 mA +25°C DC43F 0.7 1.2 mA +85°C DC47D 2.3 4.8 mA -40°C DC47E 2.3 4.
PIC24FJ256GB210 FAMILY TABLE 29-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2) DC60D 20.0 45 A -40°C DC60E 20.0 45 A +25°C DC60H 55.0 105 A +60°C DC60F 95.0 185 A +85°C DC61D 1.0 3.5 A -40°C DC61E 1.0 3.5 A +25°C DC61H 1.0 3.
PIC24FJ256GB210 FAMILY TABLE 29-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VIL Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Min Typ(1) Max Units Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.
PIC24FJ256GB210 FAMILY TABLE 29-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VOL DO10 OSCO/CLKO VOH DO20 Typ(1) Max Units Conditions — — 0.4 V IOL = 6.6mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.2V — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2.2V 3.0 — — V IOH = -3.0 mA, VDD = 3.
PIC24FJ256GB210 FAMILY TABLE 29-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. Characteristics Typ Max Units Comments VRGOUT Regulator Output Voltage — 1.8 — V VBG Internal Band Gap Reference — 1.2 — V CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 Ohm recommended; < 5 Ohm required.
PIC24FJ256GB210 FAMILY TABLE 29-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions DO50 COSCO OSCO/CLKO Pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
PIC24FJ256GB210 FAMILY TABLE 29-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial Characteristic Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC mode) DC 4 — — 32 48 MHz MHz EC ECPLL Oscillator Frequency 3.
PIC24FJ256GB210 FAMILY TABLE 29-15: INTERNAL RC ACCURACY Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No. Characteristic Min Typ Max Units Conditions F20 FRC Accuracy @ 8 MHz(1,2) -1 ±0.15 1 % -40°C TA +85°C 2.2V VDD 3.6V F21 LPRC @ 31 kHz -20 — 20 % -40°C TA +85°C VCAP (on-chip regulator output voltage) = 1.8V Note 1: 2: Frequency calibrated at 25°C and 3.3V.
PIC24FJ256GB210 FAMILY FIGURE 29-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-2 for load conditions. TABLE 29-18: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No.
PIC24FJ256GB210 FAMILY TABLE 29-19: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.2 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V AD05 VREFH Reference Voltage High AVSS + 1.
PIC24FJ256GB210 FAMILY TABLE 29-20: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 362 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC24FJ256 GB206-I/ PT e3 1020017 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 121-BGA (10x10x1.1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC24FJ256GB210 FAMILY 30.2 Package Details The following sections give the technical details of the packages.
PIC24FJ256GB210 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39975A-page 366 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39975A-page 368 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 77 . .
PIC24FJ256GB210 FAMILY ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 DS39975A-page 370 # * !( 4 ! ! & 4 % & & # & 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39975A-page 372 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 374 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY APPENDIX A: REVISION HISTORY Revision A (May 2010) Original data sheet for the PIC24FJ256GB210 family of devices. 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 376 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY INDEX A Output Compare (Double-Buffered, 16-Bit PWM Mode) ........................................... 198 PIC24F CPU Core ...................................................... 38 PIC24FJ256GB210 Family (General)......................... 19 PSV Operation (Higher Word) .................................... 76 PSV Operation (Lower Word)..................................... 76 Reset System ............................................................. 85 RTCC..............................
PIC24FJ256GB210 FAMILY CPU Arithmetic Logic Unit (ALU)......................................... 41 Control Registers ........................................................ 40 Core Registers ............................................................ 38 Programmer’s Model................................................... 37 CRC 32-Bit Programmable Cyclic Redundancy Check ..... 293 Polynomials............................................................... 294 Setup Examples for 16 and 32-Bit Polynomials .
PIC24FJ256GB210 FAMILY M Memory Organization.......................................................... 43 Microchip Internet Web Site .............................................. 382 MPLAB ASM30 Assembler, Linker, Librarian ................... 336 MPLAB Integrated Development Environment Software.................................................................... 335 MPLAB PM3 Device Programmer .................................... 338 MPLAB REAL ICE In-Circuit Emulator System.................
PIC24FJ256GB210 FAMILY CMxCON (Comparator x Control, Comparators 1-3)............................................. 314 CORCON (CPU Core Control).............................. 41, 96 CRCCON1 (CRC Control 1) ..................................... 296 CRCCON2 (CRC Control 2) ..................................... 297 CRCDATH (CRC Data High) .................................... 298 CRCDATL (CRC Data Low)...................................... 298 CRCWDATH (CRC Shift High) .................................
PIC24FJ256GB210 FAMILY SFR States.................................................................. 88 SWR (RESET Instruction)........................................... 85 TRAPR (Trap Conflict Reset)...................................... 85 UWR (Uninitialized W Register Reset) ....................... 85 WDT (Watchdog Timer Reset).................................... 85 Revision History ................................................................ 375 RTCC Alarm Configuration .............................
PIC24FJ256GB210 FAMILY NOTES: DS39975A-page 382 2010 Microchip Technology Inc.
PIC24FJ256GB210 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FJ256GB210 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24FJ256GB210 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GB2 10 T - I / PT - XXX Examples: a) PIC24FJ128GB206-I/PT: PIC24F device with USB On-The-Go, 128-KB program memory, 96-KB data memory, 64-pin, Industrial temp., TQFP package. b) PIC24FJ256GB210-I/PT: PIC24F device with USB On-The-Go, 256-KB program memory, 96-KB data memory, 100-pin, Industrial temp., TQFP package.
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