Datasheet

PIC24FJ256GB110 FAMILY
DS39897C-page 74  2009 Microchip Technology Inc.
TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type Clock Source SYSRST Delay
System Clock
Delay
Notes
POR
(6)
EC TPOR + TPWRT — 1, 2
FRC, FRCDIV TPOR + TPWRT TFRC 1, 2, 3, 6
LPRC T
POR + TPWRT TLPRC 1, 2, 3
ECPLL TPOR + TPWRT TLOCK 1, 2, 4
FRCPLL TPOR + TPWRT TFRC + TLOCK 1, 2, 3, 4
XT, HS, SOSC T
POR+ TPWRT TOST 1, 2, 5
XTPLL, HSPLL TPOR + TPWRT TOST + TLOCK 1, 2, 4, 5
BOR EC TPWRT — 2
FRC, FRCDIV T
PWRT TFRC 2, 3, 6
LPRC TPWRT TLPRC 2, 3
ECPLL TPWRT TLOCK 2, 4
FRCPLL T
PWRT TFRC + TLOCK 2, 3, 4
XT, HS, SOSC T
PWRT TOST 2, 5
XTPLL, HSPLL TPWRT TFRC + TLOCK 2, 3, 4
All Others Any Clock — — —
Note 1: T
POR = Power-on Reset delay.
2: TPWRT = 64 ms nominal if regulator is disabled (ENVREG tied to VSS).
3: T
FRC and TLPRC = RC Oscillator start-up times.
4: TLOCK = PLL lock time.
5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with
FRC, and in such cases, FRC start-up time is valid.
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.