Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 16-Bit 32 MHz I/O number 83

PIC24FJ256GB110 FAMILY

DS39897C-page 50  2009 Microchip Technology Inc.

TABLE 4-10: UART REGISTER MAPS

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

U1MODE 0220 UARTEN

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U1STA 0222 UTXISEL1 UTXINV UTXISEL0

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U1TXREG 0224

— — — — — — — Transmit Register xxxx

U1RXREG 0226

— — — — — — — Receive Register 0000

U1BRG 0228 Baud Rate Generator Prescaler Register 0000

U2MODE 0230 UARTEN

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U2STA 0232 UTXISEL1 UTXINV UTXISEL0

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U2TXREG 0234

— — — — — — — Transmit Register xxxx

U2RXREG 0236

— — — — — — — Receive Register 0000

U2BRG 0238 Baud Rate Generator Prescaler Register 0000

U3MODE 0250 UARTEN

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U3STA 0252 UTXISEL1 UTXINV UTXISEL0

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U3TXREG 0254

— — — — — — — Transmit Register xxxx

U3RXREG 0256

— — — — — — — Receive Register 0000

U3BRG 0258 Baud Rate Generator Prescaler Register 0000

U4MODE 02B0 UARTEN

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U4STA 02B2 UTXISEL1 UTXINV UTXISEL0

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U4TXREG 02B4

— — — — — — — Transmit Register xxxx

U4RXREG 02B6

— — — — — — — Receive Register 0000

U4BRG 02B8 Baud Rate Generator Prescaler Register 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-11: SPI REGISTER MAPS

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

SPI1STAT 0240 SPIEN

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI1CON1 0242

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI1CON2 0244 FRMEN SPIFSD SPIFPOL

— — — — — — — — — — — SPIFE SPIBEN 0000

SPI1BUF 0248 Transmit and Receive Buffer 0000

SPI2STAT 0260 SPIEN

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI2CON1 0262

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI2CON2 0264 FRMEN SPIFSD SPIFPOL

— — — — — — — — — — — SPIFE SPIBEN 0000

SPI2BUF 0268 Transmit and Receive Buffer 0000

SPI3STAT 0280 SPIEN

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI3CON1 0282

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI3CON2 0284 FRMEN SPIFSD SPIFPOL

— — — — — — — — — — — SPIFE SPIBEN 0000

SPI3BUF 0288 Transmit and Receive Buffer 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.