Datasheet

 2009 Microchip Technology Inc. DS39897C-page 293
PIC24FJ256GB110 FAMILY
26.2 On-Chip Voltage Regulator
All PIC24FJ256GB110 family devices power their core
digital logic at a nominal 2.5V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ256GB110 family
incorporate an on-chip regulator that allows the device
to run its core logic from V
DD.
The regulator is controlled by the ENVREG pin. Tying V DD
to the pin enables the regulator, which in turn, provides
power to the core from the other V
DD pins. When the reg-
ulator is enabled, a low-ESR capacitor (such as ceramic)
must be connected to the V DDCORE /V CAP pin
(Figure 26-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
(C
EFC ) is provided in Section 29.1 “DC Characteristics” .
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic, at a nomi-
nal 2.5V, must be supplied to the device on the
V
DDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the V
DDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 26-1 for possible
configurations.
26.2.1 VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic.
The regulator can provide this level from a VDD of about
2.5V, all the way up to the device’s V
DDMAX. It does not
have the capability to boost V
DD levels below 2.5V. In
order to prevent “brown out” conditions when the volt-
age drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows V
DD, with a typical voltage drop of 100 mV.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect circuit. When V
DD drops below full-speed oper-
ating voltage, the circuit sets the Low-Voltage Detect
Interrupt Flag, LVDIF (IFS4<8>). This can be used to
generate an interrupt and put the application into a
low-power operational mode, or trigger an orderly
shutdown.
Low-Voltage Detection (LVD) is only available when the
regulator is enabled.
FIGURE 26-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJ256GB
3.3V
(1)
2.5V
(1)
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJ256GB
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJ256GB
2.5V
(1)
Regulator Disabled (VDD tied to VDDCORE):
Note 1: These are typical operating voltages. Refer
to Section 29.1 “DC Characteristics” for
the full operating ranges of V
DD and
V
DDCORE.
(10 F typ)