Datasheet

 2009 Microchip Technology Inc. DS39897C-page 249
PIC24FJ256GB110 FAMILY
FIGURE 19-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ
AND WRITE STROBES, TWO CHIP SELECTS)
FIGURE 19-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, TWO CHIP SELECTS)
FIGURE 19-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
FIGURE 19-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PMRD
PMWR
PMD<7:0>
PMCS1
PMA<13:8>
PMALL
PMA<7:0>
PIC24F
Address Bus
Multiplexed
Data and
Address Bus
Control Lines
PMCS2
PMRD
PMWR
PMD<7:0>
PMCS1
PMALH
PMA<13:8>
PIC24F
Multiplexed
Data and
Address Bus
Control Lines
PMALL
PMCS2
PMD<7:0>
PMALH
D<7:0>
373
A<15:0>
D<7:0>
A<7:0>
373
PMRD
PMWR
OE
WR
CE
PIC24F
Address Bus
Data Bus
Control Lines
PMCS1
PMALL
A<15:8>
PMA<10:8>
D<7:0>
373
A<10:0>
D<7:0>
A<7:0>
PMRD
PMWR
OE WR
CE
PIC24F
Address Bus
Data Bus
Control Lines
PMCS1
PMALL
A<10:8>
PMD<7:0>