Datasheet

 2009 Microchip Technology Inc. DS39897C-page 121
PIC24FJ256GB110 FAMILY
8.0 OSCILLATOR
CONFIGURATION
The oscillator system for PIC24FJ256GB110 family
devices has the following features:
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• An on-chip USB PLL block to provide a stable,
48 MHz clock for the USB module as well as a range
of frequency options for the system clock
• Software-controllable switching between various
clock sources
• Software-controllable postscaler for selective
clocking of CPU for system power savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
• A separate and independently configurable system
clock output for synchronizing external hardware
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1: PIC24FJ256GB110 FAMILY CLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 6. “Oscillator” (DS39700).
PIC24FJ256GB110 Family
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
Clock Source Option
for Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
CPU
Peripherals
Postscaler
CLKDIV<10:8>
WDT, PWRT
8 MHz
FRCDIV
31 kHz (nominal)
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
Postscaler
Clock Control Logic
Fail-Safe
Clock
Monitor
CLKDIV<14:12>
FRC
CLKO
(nominal)
XTPLL, HSPLL
ECPLL,FRCPLL
8 MHz
4 MHz
PLL &
DIV
PLLDIV<2:0> CPDIV<1:0>
48 MHz USB Clock
USB PLL
Reference Clock
Generator
REFO
REFOCON<15:8>