Datasheet

© 2007 Microchip Technology Inc. DS39907A-page 9
PIC24FJXXXGA1/GB1
2.4 Memory Map
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map and supports up to 87K instruction words
(about 256 Kbytes). Table 2-2 shows the program
memory size and number of erase and program blocks
present in each device variant. Each erase block, or
page, contains 512 instructions, and each program
block, or row, contains 64 instructions.
Locations 800000h through 8007FEh are reserved for
executive code memory. This region stores the
programming executive and the debugging executive.
The programming executive is used for device pro-
gramming and the debugging executive is used for
in-circuit debugging. This region of memory can not be
used to store user code.
The last three implemented program memory locations
are reserved for the Flash Configuration Words. In
PIC24FJXXXGB1 family devices, the last three loca-
tions are used for the Configuration Words; for
PIC24FJXXXGA1 devices, the last two locations are
used. The reserved addresses are shown in Table 2-2.
Locations FF0000h and FF0002h are reserved for the
Device ID registers. These bits can be used by the
programmer to identify what device type is being
programmed. They are described in Section 6.1
“Device ID”. The Device ID registers read out
normally, even after code protection is applied.
Figure 2-9 shows the memory map for the
PIC24FJXXXGA1/GB1 family variants.
TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR
PIC24FJXXXGA1/GB1 DEVICES
Device
User Memory
Address Limit
(Instruction Words)
Write
Blocks
Erase
Blocks
Configuration Word Addresses
123
PIC24FJ64GB1XX 00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh
PIC24FJ128GA1XX
0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh
PIC24FJ128GB1XX
PIC24FJ192GA1XX
020BFEh (67K) 1048 131 020BFEh 020BFCh 020BFA
PIC24FJ192GB1XX
PIC24FJ256GA1XX
02ABFEh (87K) 1368 171 02ABFEh 02ABFCh 02ABFA
PIC24FJ256GB1XX