Datasheet

© 2007 Microchip Technology Inc. DS39907A-page 47
PIC24FJXXXGA1/GB1
6.2 Checksum Computation
Checksums for the PIC24FJXXXGA1/GB1 families are
16 bits in size. The checksum is calculated by summing
the following:
• Contents of code memory locations
• Contents of Configuration registers
Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
byte at a time, using only their native data size. More
specifically, Configuration registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
TABLE 6-4: CHECKSUM COMPUTATION
Device
Read Code
Protection
Checksum Computation
Erased
Checksum
Value
Checksum with
0xAAAAAA at 0x0
and Last Code
Address
PIC24FJ128GA106 Disabled CFGB + SUM(0:1F7F9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ192GA106 Disabled CFGB + SUM(0:20BF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ256GA106 Disabled CFGB + SUM(0:2ABF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ128GA108 Disabled CFGB + SUM(0:1F7F9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ192GA108 Disabled CFGB + SUM(0:20BF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ256GA108 Disabled CFGB + SUM(0:2ABF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ128GA110 Disabled CFGB + SUM(0:1F7F9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ192GA110 Disabled CFGB + SUM(0:20BF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ256GA110 Disabled CFGB + SUM(0:2ABF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ64GB106 Disabled CFGB + SUM(0:ABF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ128GB106 Disabled CFGB + SUM(0:1F7F9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ192GB106 Disabled CFGB + SUM(0:20BF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ256GB106 Disabled CFGB + SUM(0:2ABF9) TBD TBD
Enabled 0 TBD TBD
PIC24FJ64GB108 Disabled CFGB + SUM(0:ABF9) TBD TBD
Enabled 0 TBD TBD
Legend: Item Description
SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB = CFGB = Configuration Block (masked) Byte sum of (CW1 & 0x7BDF + CW2 & 0xF7FF +
CW3 & 0xE1FF)
TBD = To Be Determined
Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2); CW3 is (last
location – 4).