Datasheet

© 2007 Microchip Technology Inc. DS39907A-page 29
PIC24FJXXXGA1/GB1
4.6 Configuration Bits Programming
4.6.1 OVERVIEW
The PIC24FJXXXGA1/GB1 families have Configura-
tion bits stored in the last three locations of imple-
mented program memory (see Table 2-2 for locations).
These bits can be set or cleared to select various
device configurations. There are three types of Config-
uration bits: system operation bits, code-protect bits
and unit ID bits. The system operation bits determine
the power-on settings for system level components,
such as oscillator and Watchdog Timer. The
code-protect bits prevent program memory from being
read and written.
The descriptions for the Configuration bits in the Flash
Configuration Words are shown in Table 4-2.
Note: Although not implemented with a specific
function, some Configuration bit positions
have default states that must always be
maintained to ensure device functionality,
regardless of the settings of other Config-
uration bits. Refer to Table 3-7 for a list of
these bit positions and their default states.
TABLE 4-2: PIC24FJXXXGA1/GB1 CONFIGURATION BITS DESCRIPTION
Bit Field Register Description
DEBUG CW1<11> Background Debug Enable bit
1 = Device will reset in User mode
0 = Device will reset in Debug mode
DISUVREG
(1)
CW2<3> Internal USB 3.3v Regulator Disable bit
1 = Regulator is disabled
0 = Regulator is enabled
FCKSM<1:0> CW2<7:6> Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FNOSC<2:0> CW2<10:8> Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRCDIV) oscillator with postscaler
110 = Reserved
101 = Low-Power RC (LPRC) oscillator
100 = Secondary (SOSC) oscillator
011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000 = Fast RC (FRC) oscillator
FWDTEN CW1<7> Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
clearing the SWDTEN bit in the RCON register will have no effect)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
FWPSA CW1<4> Watchdog Timer Postscaler bit
1 = 1:128
0 = 1:32
GCP CW1<13> General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
GWRP CW1<12> General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
Note 1: Available on PIC24FJXXXGB1XX devices only.
2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.