Datasheet

PIC24FJXXXGA1/GB1
DS39907A-page 2 © 2007 Microchip Technology Inc.
2.1 Power Requirements
All devices in the PIC24FJXXXGA1/GB1 families are
dual voltage supply designs: one supply for the core
and peripherals and another for the I/O pins. A regula-
tor is provided on-chip to alleviate the need for two
external voltage supplies.
All PIC24FJXXXGA1/GB1 devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJXXXGA1/GB1 fami-
lies incorporate an on-chip regulator that allows the
device to run its core logic from V
DD.
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as tantalum) must
be connected to the V
DDCORE pin (Table 2-1 and
Figure 2-2). This helps to maintain the stability of the
regulator. The specifications for core voltage and capac-
itance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
2.2 Program Memory Write/Erase
Requirements
The Flash program memory on PIC24FJXXXGA1/GB1
devices has a specific write/erase requirement that
must be adhered to for proper device operation. The
rule is that any given word in memory must not be writ-
ten more than twice before erasing the page in which it
is located. Thus, the easiest way to conform to this rule
is to write all the data in a programming block within
one write cycle. The programming methods specified in
this specification comply with this requirement.
2.3 Pin Diagrams
The pin diagrams for the PIC24FJXXXGA1/GB1 fami-
lies are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
2.3.1 PGCx AND PGDx PIN PAIRS
All of the devices in the PIC24FJXXXGA1/GB1 families
have three separate pairs of programming pins,
labelled as PGEC1/PGED1, PGEC2/PGED2, and
PGEC3/PGED3. Any one of these pin pairs may be
used for device programming by either ICSP or
Enhanced ICSP. Unlike voltage supply and ground
pins, it is not necessary to connect all three pin pairs to
program the device. However, the programming
method must use both pins of the same pair.
FIGURE 2-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
Note: Writing to a location multiple times without
erasing is not recommended.
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJXXXGA1/GB1
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
(10
μF typ)
Note 1: These are typical operating voltages. Refer
to
Section 7.0 “AC/DC Characteristics and
Timing Requirements”
for the full operating
ranges of V
DD and VDDCORE.
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC24FJXXXGA1/GB1
3.3V
(1)
2.5V
(1)
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA1/GB1
2.5V
(1)
Regulator Disabled (VDD tied to VDDCORE):