Datasheet

 2008-2013 Microchip Technology Inc. DS80369P-page 5
PIC24FJ256GB110 FAMILY
6. Module: SPI (Master Mode)
In Master mode, both the SPIx Interrupt Flag
(SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may
become set one-half clock cycle early, instead of
on the clock edge. This occurs only under the
following circumstances:
• Enhanced Buffer mode is disabled (SPIBEN = 0)
• The module is configured for serial data output
changes on transition from clock active to clock
Idle state (CKE = 1)
If the application is using the interrupt flag to deter-
mine when data to be transmitted is written to the
transmit buffer, the data currently in the buffer may
be overwritten.
Work around
Before writing to the SPIx buffer, check the SCKx pin
to determine if the last clock edge has passed.
Example 1 (below) demonstrates a method for
doing this. In this example, pin, RD1, functions as
the SPIx clock, SCKx, which is configured as Idle
low.
Affected Silicon Revisions
7. Module: CTMU
When the CTMU module is selected as the trigger
source (SYNCSEL<4:0> = 11000), the output
compare or input capture module triggers may not
work.
Work around
Manually trigger the output compare and/or input
capture modules after a CTMU event is received.
Be certain to compensate for any time latency
required by manually triggering the module.
Affected Silicon Revisions
8. Module: USB
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the PRE signal may not be generated correctly.
This will result in not being able to communicate
correctly with the low-speed device.
Work around
Connect low-speed devices directly to the
application and not through a USB hub.
Affected Silicon Revisions
9. Module: USB (VUSB Regulator)
The USB internal voltage regulator does not
regulate to 3.3V. The USB internal voltage regulator
is an optional feature and is not required for USB
operation or compliance.
Work around
Disable the USB voltage regulator (DISUVREG
Configuration bit set to ‘1’) and supply 3.0V to 3.6V
from an external source to the VUSB pin.
Affected Silicon Revisions
10. Module: USB
When the module is configured to use an external
transceiver, the CRC5 value of some packets may
be incorrect.
Work around
Use the module’s internal transceiver.
Affected Silicon Revisions
EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCK
A3 A5 A6
X
A3 A5 A6
X
A3 A5 A6
XX
X
A3 A5 A6
XX
X
A3 A5
A6
XX
X
while(IFS0bits.SPI1IF == 0){} //wait for the transmission to complete
while(PORTDbits.RD1 == 1){} //wait for the last clock to finish
SPI1BUF = 0xFF; //write new data to the buffer