Datasheet

PIC24FJ256GB110 FAMILY
DS80369P-page 2  2008-2013 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A3 A5 A6
Core RAM Operation 1. Repeated register operations entering Doze mode. X X X
Core BOR 2. Spontaneous BOR with analog or USB peripherals. X
JTAG Device
Programming
3. Programming lockout during JTAG programming. X X X
UART — 4. Framing issues when using two Stop bits. X
I/O PORTB 5. RB5 remains in high-impedance in Open-Drain mode. X
SPI Master mode 6. SPIxIF and SPIRBF may be set early in some
instances.
X
CTMU — 7. Trigger to IC or OC modules may not work. X
USB — 8. Issue with Host mode, low-speed operation. X X X
USB V
USB Regulator 9. Does not regulate to 3.3V. X X X
USB — 10. CRC errors while using external transceiver. X X X
USB — 11. ACTIVIF flag functions only during Sleep. X X X
UART UERIF
Interrupt
12. Interrupt may not function with multiple errors. X
UART FIFO Error 13. PERR and FERR flags may be incorrect in certain
cases.
X
UART IrDA
®
14. Payload error in 8-bit mode. X
UART IrDA 15. Framing error in 9-bit mode. X
UART IrDA 16. Payload errors in 8-bit mode. X
I
2
C™
Module
Master mode 17. Master module may Acknowledge its own
transmission as a slave.
X
I
2
C
Module
Slave mode 18. Module may not respond correctly to reserved
addresses.
X
Memory PSV 19. False address error traps. X
ICSP™ — 20. PGEC3/PGED3 not functional. X
Core Instruction Set 21. Issue with Read-After-Write stalls in REPEAT loops. X X X
RTCC — 22. Unexpected decrements of Alarm Repeat Counter. X
SPI Enhanced
Buffer mode
23. Issue with early full buffer interrupt. X
A/D — 24. Disabled voltage references during Debug mode
(64-pin devices only).
X
SPI Enhanced
Buffer mode
25. Issue with SRMPT bit becoming set early in certain
cases.
X
Core Code-Protect 26. GCP disables write access to interrupt vectors. X
CTMU A/D Trigger 27. Automatic conversion may not function. X
Oscillator LPRC 28. Failure to restart following BOR events. X
Oscillator Two-Speed
Start-up
29. Feature is not functional. X X X
Output
Compare
— 30. Single missed compare events under certain
conditions.
X
Interrupts INTx 31. External interrupts missed when writing to INTCON2. X X X
A/D
Converter
— 32. Module continues to draw current when disabled. X X X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.