Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 64 Exposed Pad (9x9) 16-Bit 32 MHz I/O number 51

 2008-2013 Microchip Technology Inc. DS80369P-page 1

PIC24FJ256GB110 FAMILY

The PIC24FJ256GB110 family devices that you have

received conform functionally to the current Device Data

Sheet (DS39897C), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC24FJ256GB110 family

silicon.

Data Sheet Clarifications and corrections start on

page 14, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2

programmer/debugger or to the PICkit 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB IDE hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various

PIC24FJ256GB110 family silicon revisions are shown

in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A6).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number

Device

(1)

Revision ID for

Silicon Revision

(2)

Part Number

Device

(1)

Revision ID for

Silicon Revision

(2)

A3 A5 A6 A3 A5 A6

PIC24FJ256GB110 101Fh

01h 03h 04h

PIC24FJ128GB108 100Bh

01h 03h 04h

PIC24FJ192GB110 1017h PIC24FJ64GB108 1003h

PIC24FJ128GB110 100Fh PIC24FJ256GB106 1019h

PIC24FJ64GB110 1007h PIC24FJ192GB106 1011h

PIC24FJ256GB108 101Bh PIC24FJ128GB106 1009h

PIC24FJ192GB108 1013h PIC24FJ64GB106 1001h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format, “DEVID DEVREV”.

2: Refer to the “PIC24FJXXXGA0XX Flash Programming Specification” (DS39768) for detailed information

on Device and Revision IDs for your specific device.

PIC24FJ256GB110 Family

Silicon Errata and Data Sheet Clarification

Summary of content (22 pages)

PAGE 1
PIC24FJ256GB110 FAMILY PIC24FJ256GB110 Family Silicon Errata and Data Sheet Clarification The PIC24FJ256GB110 family devices that you have received conform functionally to the current Device Data Sheet (DS39897C), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC24FJ256GB110 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A3 A5 A6 X X X X Core RAM Operation 1. Repeated register operations entering Doze mode. X Core BOR 2. Spontaneous BOR with analog or USB peripherals. X JTAG Device Programming 3. Programming lockout during JTAG programming. X 4. Framing issues when using two Stop bits. X UART — I/O PORTB 5. RB5 remains in high-impedance in Open-Drain mode.
PAGE 3
PIC24FJ256GB110 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature Item Number Affected Revisions(1) Issue Summary A3 A5 A6 Oscillator — 33. POSCEN bit does not work with Primary + PLL modes. X X X Output Compare Interrupt 34. Interrupt flag may precede the output pin change under certain circumstances. X X X CTMU — 35. Disabling module affects band gap. X X X UART Transmit 36. A TX interrupt may occur before the data transmission is complete.
PAGE 4
PIC24FJ256GB110 FAMILY Silicon Errata Issues Note: 3. Module: JTAG (Device Programming) The JTAGEN Configuration bit can be programmed to ‘0’ while using the JTAG interface for device programming. This may cause a situation where JTAG programming can lock itself out of being able to program the device. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.
PAGE 5
PIC24FJ256GB110 FAMILY 6. Module: SPI (Master Mode) 8. Module: USB In Master mode, both the SPIx Interrupt Flag (SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may become set one-half clock cycle early, instead of on the clock edge. This occurs only under the following circumstances: While operating in Host mode and attached to a low-speed device through a full-speed USB hub, the PRE signal may not be generated correctly. This will result in not being able to communicate correctly with the low-speed device.
PAGE 6
PIC24FJ256GB110 FAMILY 11. Module: USB 12. Module: UART (UERIF Interrupt) The Bus Activity Interrupt Flag, ACTVIF, is active only while the device is in Sleep mode. It will not become set when the microcontroller is in a Run mode. The UARTx error interrupt may not occur, or occur at an incorrect time, if multiple errors occur during a short period of time. Work around Read the error flags in the UxSTA register whenever a byte is received to verify the error status.
PAGE 7
PIC24FJ256GB110 FAMILY 15. Module: UART (IrDA) When the UARTx is operating in 8-bit mode (PDSEL<1:0> = 0x) and using the IrDA endec (IREN = 1), a framing error may occur when transmitting a data payload of 00h. Work around: Affected Silicon Revisions A5 • Clear the A10M bit (I2CxCON<10> = 0) prior to performing a Master mode transmit. • Read the ADD10 bit (I2CxSTAT<8>) to check for a full 10-bit match whenever a slave I2C interrupt occurs on the master module. Affected Silicon Revisions None.
PAGE 8
PIC24FJ256GB110 FAMILY 19. Module: Memory (Program Space Visibility) When accessing data in the PSV area of data RAM, it is possible to generate a false address error trap condition by reading data located precisely at the lower address boundary (8000h). If data is read using an instruction with an auto-decrement, the resulting RAM address will be below the PSV boundary (i.e., at 7FFEh); this will result in an address error trap.
PAGE 9
PIC24FJ256GB110 FAMILY 23. Module: SPI (Enhanced Buffer Modes) If the SPIx event interrupt is configured to occur when the enhanced FIFO buffer is full (SISEL<2:0> = 111), the interrupt may actually occur when the 7th byte is written to the buffer, instead of the 8th byte. The other enhanced buffer interrupts function as previously described. Work around Do not use the Full Buffer Interrupt mode.
PAGE 10
PIC24FJ256GB110 FAMILY 28. Module: Oscillator (LPRC) The LPRC may not automatically restart following BOR events (i.e., when supply voltage sags to between the BOR and POR thresholds, then returns to above the BOR level). When this happens, systems that use the LPRC clock may not work. This includes the PLL, Two-Speed Start-up, Fail-Safe Clock Monitor and the WDT. Work around For PLL issues: select a non-PLL Clock mode as the initial start-up mode, using the FNOSC Configuration bits (CW2<10:8>).
PAGE 11
PIC24FJ256GB110 FAMILY 32. Module: A/D Converter Once the A/D module is enabled (AD1CON1<15> = 1), it may continue to draw extra current, even if the module is later disabled (AD1CON1<15> = 0). Work around In addition to disabling the module through the ADON bit, set the corresponding PMD bit (ADC1MD, PMD1<0>) to power it down completely. Disabling the A/D module through the PMD register also disables the AD1PCFG registers, which in turn affects the state of any port pins with analog inputs.
PAGE 12
PIC24FJ256GB110 FAMILY 36. Module: UART 37. Module: USB (Device Mode) When using UTXISEL<1:0> = 01 (interrupt when last character is shifted out of the Transmit Shift Register), and the final character is being shifted out through the Transmit Shift Register, the TX interrupt may occur before the final bit is shifted out.
PAGE 13
PIC24FJ256GB110 FAMILY 38. Module: USB (Device and Host Modes) In previous literature for this module, the ACTVIF interrupt flag (U1OTGIR<4>) is described as being asserted, based on state changes detected on D+, D- or VBUS, when the microcontroller is in Sleep mode. In actual implementation, state changes on the RF3/USBID pin also cause the ACTVIF flag to be asserted.
PAGE 14
PIC24FJ256GB110 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39897C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. 1. Module: Guidelines for Getting Started with 16-Bit Microcontrollers Section 2.
PAGE 15
PIC24FJ256GB110 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PAGE 16
PIC24FJ256GB110 FAMILY 2. Module: Electrical Specifications The “Absolute Maximum Ratings” listed on page 311 are amended by adding the following specification: 3. Module: Electrical Specifications (DC Characteristics) Figure 29-1 (“PIC24FJ256GB110 Family Voltage-Frequency Graph”) is amended by adding an additional footnote. The updated figure is shown below (changes in bold; bold in original removed for clarity). Voltage on VUSB with respect to VSS................... (VDDCORE – 0.3V) to 4.
PAGE 17
PIC24FJ256GB110 FAMILY 4. Module: Electrical Specifications (DC Characteristics) 5. Module: Electrical Specifications In Table 29-3 (“DC Characteristics: Temperature and Voltage Specifications”), the Minimum and Maximum values for DC18 (BOR Voltage on VDD Transition) are changed to 1.80V and 2.25V, respectively. The Typical value remains unchanged. Table 29-3 (“DC Characteristics: Temperature and Voltage Specifications”) is amended by adding a new specification, VUSB, and an explanatory footnote.
PAGE 18
PIC24FJ256GB110 FAMILY 6. Module: Electrical Specifications Table 29-7 (I/O Pin Input Specifications) is amended by the addition of the following new specifications: • DI31 (Maximum Load Current for Internal Pull-up) • DI60 (Injection Currents) The new specifications, and accompanying new footnotes, 5 through 9, are shown below (additions in bold; bold in existing text was removed for clarity).
PAGE 19
PIC24FJ256GB110 FAMILY 7. Module: Electrical Specifications Table 29-10 and Table 29-11 (shown below) are added to Section 28 “Electrical Characteristics”, following the existing Table 29-9 (Program Memory). All subsequent tables in this section are renumbered accordingly. (Bold text in these tables represents original and unmodified content.) TABLE 29-10: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No.
PAGE 20
PIC24FJ256GB110 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (2/2008) Original version of this document, for silicon revision A3. Includes silicon issues 1 (Core, RAM Operation), 2 (Core, BOR), 3 (JTAG, Programming), 4 (UART), 5 (I/O, PORTB), 6 (SPI, Master Mode), 7 (Input Capture) and 8 through 11 (USB). Rev B Document (7/2008) Revised silicon issues 4 (UART) and 6 (SPI, Master Mode) to reflect updated definition of issues.
PAGE 21
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 22
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