Datasheet

 2010 Microchip Technology Inc. DS39905E-page 67
PIC24FJ256GA110 FAMILY
TABLE 6-1: RESET FLAG BIT OPERATION
6.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 8.0 “Oscillator Configuration” for
further details.
TABLE 6-2: OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST
delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST
signal is released.
Flag Bit Setting Event Clearing Event
TRAPR (RCON<15>) Trap Conflict Event POR
IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR
CM (RCON<9>) Configuration Mismatch Reset POR
EXTR (RCON<7>) MCLR
Reset POR
SWR (RCON<6>) RESET Instruction POR
WDTO (RCON<4>) WDT Time-out PWRSAV Instruction, POR,
CLRWDT
SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR
IDLE (RCON<2>) PWRSAV #IDLE Instruction POR
BOR (RCON<1>) POR, BOR —
POR (RCON<0>) POR —
Note: All Reset flag bits may be set or cleared by the user software.
Reset Type Clock Source Determinant
POR FNOSC Configuration bits
(CW2<10:8>)
BOR
MCLR COSC Control bits
(OSCCON<14:12>)
WDTO
SWR