Datasheet

PIC24FJ256GA110 FAMILY
DS39905E-page 30  2010 Microchip Technology Inc.
FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
Instruction
Decode &
Control
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
Instruction Reg
16
16 x 16
W Register Array
Divide
Support
ROM Latch
16
EA MUX
RAGU
WAGU
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data RAM
Address
Latch
Control Signals
to Various Blocks
Program Memory
Data Latch
Address Bus
16
Literal Data
16
16
Hardware
Multiplier
16
To Peripheral Modules
Address Latch
PCH PCL