Datasheet

 2010 Microchip Technology Inc. DS39905E-page 163
PIC24FJ256GA110 FAMILY
13.0 INPUT CAPTURE WITH
DEDICATED TIMER
Devices in the PIC24FJ256GA110 family all feature
9 independent enhanced input capture modules. Each
of the modules offers a wide range of configuration and
operating options for capturing external pulse events
and generating interrupts.
Key features of the enhanced output module include:
• Hardware-configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 30 user-selectable
trigger/sync sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to 6 clock sources available for each module,
driving a separate internal 16-bit counter
The module is controlled through two registers: ICxCON1
(Register 13-1) and ICxCON2 (Register 13-2). A general
block diagram of the module is shown in Figure 13-1.
13.1 General Operating Modes
13.1.1 SYNCHRONOUS AND TRIGGER
MODES
By default, the enhanced input capture module oper-
ates in a free-running mode. The internal 16-bit counter
ICxTMR counts up continuously, wrapping around from
FFFFh to 0000h on each overflow, with its period
synchronized to the selected external clock source.
When a capture event occurs, the current 16-bit value
of the internal counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Standard, free-running operation is selected by setting
the SYNCSEL bits to ‘00000’ and clearing the ICTRIG
bit (ICxCON2<7>). Synchronous and Trigger modes
are selected any time the SYNCSEL bits are set to any
value except ‘00000’. The ICTRIG bit selects either
Synchronous or Trigger mode; setting the bit selects
Trigger mode operation. In both modes, the SYNCSEL
bits determine the sync/trigger source.
When the SYNCSEL bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
FIGURE 13-1: INPUT CAPTURE BLOCK DIAGRAM
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 34. “Input Capture with
Dedicated Timer” (DS39722)
ICxBUF
4-Level FIFO Buffer
ICx Pin
(1)
ICM<2:0>
Set ICxIF
Edge Detect Logic
ICI<1:0>
(1)
ICOV, ICBNE
Interrupt
Logic
System Bus
Prescaler
Counter
1:1/4/16
and
Clock Synchronizer
Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
Event and
Trigger and
Sync Logic
Clock
Select
IC Clock
Sources
Trigger and
Sync Sources
ICTSEL<2:0>
SYNCSEL<4:0>
TRIGGER
16
16
16
ICxTMR
Increment
Reset