Datasheet

PIC24FJ256GA110 FAMILY
DS39905E-page 14  2010 Microchip Technology Inc.
FIGURE 1-1: PIC24FJ256GA110 FAMILY GENERAL BLOCK DIAGRAM
Instruction
Decode &
Control
16
16
Program Counter
16-Bit ALU
23
24
Data Bus
Inst Register
16
Divide
Support
Inst Latch
16
EA MUX
Read AGU
Write AGU
16
16
8
Interrupt
Controller
PSV & Table
Data Access
Control Block
Stack
Control
Logic
Repeat
Control
Logic
Data Latch
Data RAM
Address
Latch
Address Latch
Program Memory
Data Latch
16
Address Bus
Literal Data
23
Control Signals
16
16
16 x 16
W Reg Array
Multiplier
17x17
OSCI/CLKI
OSCO/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
Precision
Reference
Band Gap
FRC/LPRC
Oscillators
Regulator
Voltage
VDDCORE/VCAP
ENVREG
PORTA
(1)
PORTC
(1)
(13 I/O)
(8 I/O)
PORTB
(16 I/O)
Note 1:
Not all I/O pins or features are implemented on all device pinout configurations. See Ta bl e 1 - 4 for specific implementations by pin count .
2: BOR functionality is provided when the on-board voltage regulator is enabled.
3: These peripheral I/Os are only accessible through remappable pins.
PORTD
(1)
(16 I/O)
Comparators
(3)
Timer2/3
(3)
Timer1
RTCC
IC
ADC
10-Bit
PWM/OC SPI
I2C
Timer4/5
(3)
PMP/PSP
1-9
(3)
ICNs
(1)
UART
LVD
(2)
REFO
PORTE
(1)
PORTG
(1)
(10 I/O)
(12 I/O)
PORTF
(1)
(11 I/O)
1/2/3
(3)
1/2/3
1/2/3/4
(3)
1-9
(3)
CTMU
PCH PCL