PIC24FJ256GA110 Family Data Sheet 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC24FJ256GA110 FAMILY 64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Pin Select Power Management: Peripheral Features: • On-Chip 2.5V Voltage Regulator • Switch between Clock Sources in Real Time • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up • Run mode: 1 mA/MIPS, 2.0V Typical • Standby Current with 32 kHz Oscillator: 2.6 A, 2.
PIC24FJ256GA110 FAMILY • Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with On-Chip Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Brown-out Reset (BOR) • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protec
PIC24FJ256GA110 FAMILY CN63/PMD5/RE5 RP22/CN52/PMBE/RD3 RP23/CN51/RD2 RP24/CN50/RD1 65 64 63 62 61 RP20/CN14/PMRD/RD5 RP25/CN13/PMWR/RD4 CN19/RD13 RPI42/CN57/RD12 VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 ENVREG CN68/RF0 75 74 73 72 71 70 69 68 67 66 CN59/PMD1/RE1 CN58/PMD0/RE0 CN77/RG0 CN78/RG1 CN69/RF1 CN60/PMD2/RE2 80 79 78 77 76 CN62/PMD4/RE4 CN61/PMD3/RE3 Pin Diagram (80-Pin TQFP) SCL3/CN64/PMD6/RE6 2 SDA3/CN65/PMD7/RE7 3 RPI38/CN45/RC1 4 RPI40/CN47/RC3 5 59 SOSCO/C3INC/ RPI37/T
PIC24FJ256GA110 FAMILY 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CN62/PMD4/RE4 CN61/PMD3/RE3 CN60/PMD2/RE2 CN80/RG13 CN79/RG12 CN81/RG14 CN59/PMD1/RE1 CN58/PMD0/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 CN69/RF1 CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 RP20/CN14/PMRD/RD5 RP25/CN13/PMWR/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/CN52/PMBE/RD3 RP23/CN51/RD2 RP24/CN50/RD1 Pin Diagram (100-Pin TQFP) CN82/RG15 1 75 VDD 2 74 VSS SOSCO/C3INC/ RPI37/T1CK/CN0/RC14
PIC24FJ256GA110 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 23 3.0 CPU ...................................................................................................
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PIC24FJ256GA110 FAMILY 1.
PIC24FJ256GA110 FAMILY 1.2 Other Special Features • Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ256GA110 family incorporates a range of serial communication peripherals to handle a range of application requirements.
PIC24FJ256GA110 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GA110 FAMILY: 64-PIN DEVICES Features PIC24FJ64GA106 PIC24FJ128GA106 PIC24FJ192GA106 PIC24FJ256GA106 Operating Frequency Program Memory (bytes) Program Memory (instructions) DC – 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins Remappable Pins 53 31 (29 I/O, 2 input only) Timers: 5(1) To
PIC24FJ256GA110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GA110 FAMILY: 80-PIN DEVICES Features PIC24FJ64GA108 PIC24FJ128GA108 PIC24FJ192GA108 PIC24FJ256GA108 Operating Frequency Program Memory (bytes) Program Memory (instructions) DC – 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) I/O Ports 192K 66 (62/4) Ports A, B, C, D, E, F, G Total I/O Pins Remappable Pins 69 42 (31 I/O, 11 input only) Timers: 5(1) T
PIC24FJ256GA110 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GA110 FAMILY: 100-PIN DEVICES Features PIC24FJ64GA110 PIC24FJ128GA110 PIC24FJ192GA110 PIC24FJ256GA110 Operating Frequency Program Memory (bytes) Program Memory (instructions) DC – 32 MHz 64K 128K 192K 256K 22,016 44,032 67,072 87,552 Data Memory (bytes) 16,384 Interrupt Sources (soft vectors/NMI traps) I/O Ports 66 (62/4) Ports A, B, C, D, E, F, G Total I/O Pins Remappable Pins 85 46 (32 I/O, 14 input only) Timers: 5(1)
PIC24FJ256GA110 FAMILY FIGURE 1-1: PIC24FJ256GA110 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (13 I/O) 16 16 8 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch PORTC(1) Program Memory (8 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTD(1) (16 I/O) Inst Register Instruction Decode
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer AN0 16 20 25 I ANA AN1 15 19 24 I ANA AN2 14 18 23 I ANA AN3 13 17 22 I ANA AN4 12 16 21 I ANA AN5 11 15 20 I ANA AN6 17 21 26 I ANA AN7 18 22 27 I ANA AN8 21 27 32 I ANA AN9 22 28 33 I ANA AN10 23 29 34 I ANA AN11 24 30 35 I ANA AN12 27 33 41 I ANA AN13 28 34 42 I ANA AN14
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN0 48 60 74 I ST CN1 47 59 73 I ST CN2 16 20 25 I ST CN3 15 19 24 I ST CN4 14 18 23 I ST CN5 13 17 22 I ST CN6 12 16 21 I ST CN7 11 15 20 I ST CN8 4 6 10 I ST CN9 5 7 11 I ST CN10 6 8 12 I ST CN11 8 10 14 I ST CN12 30 36 44 I ST CN13 52 66 81 I ST CN14 53 67
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN43 — 52 66 I ST CN44 — 53 67 I ST CN45 — 4 6 I ST CN46 — — 7 I ST CN47 — 5 8 I ST CN48 — — 9 I ST CN49 46 58 72 I ST CN50 49 61 76 I ST CN51 50 62 77 I ST CN52 51 63 78 I ST CN53 42 54 68 I ST CN54 43 55 69 I ST CN55 44 56 70 I ST CN56 45 57 71 I ST CN57 — 6
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CTED1 28 34 42 I ANA CTED2 27 33 41 I ANA CTPLS 29 35 43 O — CTMU Pulse Output. CVREF 23 29 34 O — Comparator Voltage Reference Output. Function Description CTMU External Edge Input 1. CTMU External Edge Input 2. ENVREG 57 71 86 I ST Voltage Regulator Enable. INT0 35 45 55 I ST External Interrupt Input.
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer RA0 — — 17 I/O ST RA1 — — 38 I/O ST RA2 — — 58 I/O ST RA3 — — 59 I/O ST RA4 — — 60 I/O ST RA5 — — 61 I/O ST RA6 — — 91 I/O ST RA7 — — 92 I/O ST RA9 — 23 28 I/O ST RA10 — 24 29 I/O ST RA14 — 52 66 I/O ST RA15 — 53 67 I/O ST RB0 16 20 25 I/O ST RB1 15 19 24 I/O ST
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description RD0 46 58 72 I/O ST RD1 49 61 76 I/O ST RD2 50 62 77 I/O ST RD3 51 63 78 I/O ST RD4 52 66 81 I/O ST RD5 53 67 82 I/O ST RD6 54 68 83 I/O ST RD7 55 69 84 I/O ST RD8 42 54 68 I/O ST RD9 43 55 69 I/O ST RD10 44 56 70 I/O ST RD11 45 57 71 I/O ST RD12 —
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer RG0 — 75 90 I/O ST RG1 — 74 89 I/O ST RG2 37 47 57 I/O ST RG3 36 46 56 I/O ST RG6 4 6 10 I/O ST RG7 5 7 11 I/O ST RG8 6 8 12 I/O ST RG9 8 10 14 I/O ST RG12 — — 96 I/O ST RG13 — — 97 I/O ST RG14 — — 95 I/O ST RG15 — — 1 I/O ST RP0 16 20 25 I/O ST RP1 15 19
PIC24FJ256GA110 FAMILY TABLE 1-4: PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP, QFN 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description RPI32 — — 40 I ST RPI33 — 13 18 I ST Remappable Peripheral (input only).
PIC24FJ256GA110 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24F J devices only) (see Section 2.
PIC24FJ256GA110 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24FJ256GA110 FAMILY 2.4 Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) Note: This section applies only to PIC24F J devices with an on-chip voltage regulator. The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground.
PIC24FJ256GA110 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC24FJ256GA110 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24FJ256GA110 FAMILY 2.7 Configuration of Analog and Digital Pins During ICSP Operations If an ICSP compliant emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins. Depending on the particular device, this is done by setting all bits in the ADnPCFG register(s), or clearing all bit in the ANSx registers. All PIC24F devices will have either one or more ADnPCFG registers or several ANSx registers (one for each port); no device will have both.
PIC24FJ256GA110 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 2. “CPU” (DS39703). The PIC24F CPU has a 16-bit (data), modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24FJ256GA110 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 Literal Data Instruction Decode & Control 16 16 x 16 W Registe
PIC24FJ256GA110 FAMILY TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 W
PIC24FJ256GA110 FAMILY 3.
PIC24FJ256GA110 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 R/C-0 (1) — IPL3 R/W-0 U-0 U-0 PSV — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt pri
PIC24FJ256GA110 FAMILY 3.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
PIC24FJ256GA110 FAMILY 4.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space The program address memory space of the PIC24FJ256GA110 family devices is 4M instructions.
PIC24FJ256GA110 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In PIC24FJ256GA110 family devices, the top three words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ256GA110 family are shown in Table 4-1. Their location in the memory map is shown with the other memory vectors in Figure 4-1.
PIC24FJ256GA110 FAMILY 4.2 Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words.
PIC24FJ256GA110 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A Sign-Extend (SE) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations.
2010 Microchip Technology Inc.
ICN REGISTER MAP File Addr Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 0 All Resets CNPD1 0054 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CNPD2 0056 CN31PDE CN30PDE CN29PDE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN1PDE CN0PDE 0000 CN17PDE CN16PDE 0000 CNPD3 0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2) CN32PDE 0000 Bit 11 Bit 10 Bit 9 B
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File Name Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TMR1 0100 Timer1 Register 0000 PR1 0102 Timer1 Period Register FFFF T1CON 0104 TMR2 0106 TON Timer2 Register TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) 0000 TMR3 010A Timer3 Register 0000 — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 0000 PR2 010C Timer2 Period Re
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File Name Addr OC1CON1 0190 OUTPUT COMPARE REGISTER MAP Bit 15 — OC1CON2 0192 FLTMD Bit 14 Bit 13 — OCSIDL FLTOUT FLTTRIEN Bit 12 Bit 11 Bit 10 OCTSEL2 OCTSEL1 OCTSEL0 OCINV — — Bit 9 Bit 8 — — — OC32 Bit 7 Bit 6 ENFLT0 — OCTRIG TRIGSTAT Bit 5 — OCTRIS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC1RS 0194 Output Compare 1 Secondary Register 0000 OC1R 0196 Output Compare 1 Regist
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UART REGISTER MAP File Name Addr U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 U1TXREG 0224 — U1RXREG 0226 — U1BRG 0228 U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U2TXREG 0234 — — — — — — — Transmit Register xxxx U2RXREG 0236 — — — — — — — Receive Register 0000 U2BRG 0238 U3MODE 0250 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U3STA 0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXE
2010 Microchip Technology Inc.
File Name PORTE REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 8(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISE 02E0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF PORTE 02E2 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx LATE 02E4 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx ODCE 02E6 — — — — — —
2010 Microchip Technology Inc.
PARALLEL MASTER/SLAVE PORT REGISTER MAP File Name Addr Bit 15 PMCON 0600 PMPEN — PSIDL CSF1 CSF0 ALP CS2P CS1P BEP PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 PMADDR 0604 CS2 CS1 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 All
2010 Microchip Technology Inc.
File Name SYSTEM REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IDLE BOR Bit 0 All Resets RCON 0740 TRAPR IOPUWR — — — — CM PMSLP EXTR SWR SWDTEN WDTO SLEEP OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 REFOCON
PIC24FJ256GA110 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear.
PIC24FJ256GA110 FAMILY TABLE 4-30: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0> Data EA<14:0>(1)
PIC24FJ256GA110 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
PIC24FJ256GA110 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
PIC24FJ256GA110 FAMILY 5.0 Note: RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time and erase program memory in blocks of 512 instructions (1536 bytes) at a time. FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ256GA110 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively.
PIC24FJ256GA110 FAMILY REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Set Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Wr
PIC24FJ256GA110 FAMILY 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is as follows: 1. 2. 3. 4. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
PIC24FJ256GA110 FAMILY EXAMPLE 5-2: ERASING A PROGRAM MEMORY BLOCK (C LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; unsigned int offset; // Address of row to write //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize
PIC24FJ256GA110 FAMILY EXAMPLE 5-4: LOADING THE WRITE BUFFERS (C LANGUAGE CODE) // C example using MPLAB C30 #define NUM_INSTRUCTION_PER_ROW 64 unsigned int offset; unsigned int i; unsigned long progAddr = 0xXXXXXX; unsigned int progData[2*NUM_INSTRUCTION_PER_ROW]; //Set up NVMCON for row programming NVMCON = 0x4001; // Address of row to write // Buffer of data to write // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary
PIC24FJ256GA110 FAMILY 5.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to ‘0011’. The write is performed by executing the unlock sequence and setting the WR bit, as shown in Example 5-7. An equivalent procedure in C, using the MPLAB C30 compiler and built-in hardware functions, is shown in Example 5-8.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 64 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 7. “Reset” (DS39712). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24FJ256GA110 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 — U-0 — U-0 — U-0 — R/W-0 CM R/W-0 PMSLP bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9 bit 8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TRAPR: Trap Reset Flag bit 1 = A Trap C
PIC24FJ256GA110 FAMILY TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR IDLE (RCON<2>) PWRSAV #IDLE Instruction POR PWRSAV Instruction, POR, CLRWDT BOR (RCON<1
PIC24FJ256GA110 FAMILY TABLE 6-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type POR(6) Clock Source EC BOR All Others SYSRST Delay System Clock Delay TPOR + TPWRT + TRST — Notes 1, 2, 7 FRC, FRCDIV TPOR + TPWRT + TRST TFRC 1, 2, 3, 7 LPRC TPOR + TPWRT + TRST TLPRC 1, 2, 3, 7 1, 2, 4, 7 ECPLL TPOR + TPWRT + TRST TLOCK FRCPLL TPOR + TPWRT + TRST TFRC + TLOCK XT, HS, SOSC TPOR + TPWRT + TRST TOST XTPLL, HSPLL TPOR + TPWRT + TRST TOST + TLOCK 1, 2, 3, 4, 7 1, 2, 5, 7 1, 2
PIC24FJ256GA110 FAMILY 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 70 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU.
PIC24FJ256GA110 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap V
PIC24FJ256GA110 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations AIVT Address Flag Enable 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> IFS4<3> IEC4<3> IPC16<14:12> IFS4<13> IEC4<13> IPC19<6:4> Vector Number IVT Address ADC1 Conversion Done 13 Comparator Event 18 CRC Generator 67 00009Ah 00019Ah CTMU Event 77 0000AEh 0001AEh External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Inter
PIC24FJ256GA110 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations AIVT Address Flag Enable Priority 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0> UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 11 00002Ah 000
PIC24FJ256GA110 FAMILY REGISTER 7-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 IPL2 (2,3) R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CP
PIC24FJ256GA110 FAMILY REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting
PIC24FJ256GA110 FAMILY REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector
PIC24FJ256GA110 FAMILY REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 T2IF bit 7 R/W-0 OC2IF R/W-0 IC2IF U-0 — R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF R/W-0 INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read
PIC24FJ256GA110 FAMILY REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2TXIF bit 15 R/W-0 U2RXIF R/W-0 IC8IF bit 7 R/W-0 IC7IF bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 INT2IF U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 U = Unimplement
PIC24FJ256GA110 FAMILY REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIF: Parallel Master
PIC24FJ256GA110 FAMILY REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 — INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit
PIC24FJ256GA110 FAMILY REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIF — — — — LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt reque
PIC24FJ256GA110 FAMILY REGISTER 7-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 — bit 15 U-0 — R/W-0 IC9IF R/W-0 OC9IF R/W-0 SPI3IF R/W-0 SPF3IF R/W-0 U4TXIF R/W-0 U4ERIF bit 7 U-0 — R/W-0 MI2C3IF R/W-0 SI2C3IF R/W-0 U3TXIF R/W-0 U3RXIF R/W-0 U3ERIF bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 R/W-0 U4RXIF bit 8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit,
PIC24FJ256GA110 FAMILY REGISTER 7-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, r
PIC24FJ256GA110 FAMILY REGISTER 7-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2TXIE bit 15 R/W-0 U2RXIE R/W-0 IC8IE bit 7 R/W-0 IC7IE bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 — bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 INT2IE(1) U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 INT1IE(1) R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimpl
PIC24FJ256GA110 FAMILY REGISTER 7-12: bit 1 bit 0 Note 1: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.
PIC24FJ256GA110 FAMILY REGISTER 7-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 PMPIE: Parallel Mas
PIC24FJ256GA110 FAMILY REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 — R/W-0 INT4IE (1) R/W-0 (1) INT3IE U-0 U-0 R/W-0 R/W-0 U-0 — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enabl
PIC24FJ256GA110 FAMILY REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt reques
PIC24FJ256GA110 FAMILY REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 — bit 15 U-0 — R/W-0 IC9IE R/W-0 OC9IE R/W-0 SPI3IE R/W-0 SPF3IE R/W-0 U4TXIE R/W-0 U4ERIE bit 7 U-0 — R/W-0 MI2C3IE R/W-0 SI2C3IE R/W-0 U3TXIE R/W-0 U3RXIE R/W-0 U3ERIE bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 R/W-0 U4RXIE bit 8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bi
PIC24FJ256GA110 FAMILY REGISTER 7-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T
PIC24FJ256GA110 FAMILY REGISTER 7-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC2IP2 IC2IP1 IC2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interru
PIC24FJ256GA110 FAMILY REGISTER 7-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ256GA110 FAMILY REGISTER 7-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Conversion Complete Inte
PIC24FJ256GA110 FAMILY REGISTER 7-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ256GA110 FAMILY REGISTER 7-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC8IP2 IC8IP1 IC8IP0 — IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input C
PIC24FJ256GA110 FAMILY REGISTER 7-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — OC3IP2 OC3IP1 OC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interru
PIC24FJ256GA110 FAMILY REGISTER 7-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14
PIC24FJ256GA110 FAMILY REGISTER 7-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Pri
PIC24FJ256GA110 FAMILY REGISTER 7-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — IC3IP2 IC3IP1 IC3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capt
PIC24FJ256GA110 FAMILY REGISTER 7-27: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC7IP2 OC7IP1 OC7IP0 — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12
PIC24FJ256GA110 FAMILY REGISTER 7-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — PMPIP2 PMPIP1 PMPIP0 — OC8IP2 OC8IP1 OC8IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrup
PIC24FJ256GA110 FAMILY REGISTER 7-29: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 E
PIC24FJ256GA110 FAMILY REGISTER 7-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4
PIC24FJ256GA110 FAMILY REGISTER 7-31: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits
PIC24FJ256GA110 FAMILY REGISTER 7-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CR
PIC24FJ256GA110 FAMILY REGISTER 7-33: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 LVDIP<2:0>: Low-Voltage Detect Interrupt Priority bits 111 = I
PIC24FJ256GA110 FAMILY REGISTER 7-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP<2:0>
PIC24FJ256GA110 FAMILY REGISTER 7-36: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U4ERIP2 U4ERIP1 U4ERIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C3IP2 MI2C3IP1 MI2C3IP0 — SI2C3IP2 SI2C3IP1 SI2C3PI0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U4ERI
PIC24FJ256GA110 FAMILY REGISTER 7-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI3IP2 SPI3IP1 SPI3IP0 — SPF3IP2 SPF3IP1 SPF3IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’
PIC24FJ256GA110 FAMILY REGISTER 7-38: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC9IP2 IC9IP1 IC9IP0 — OC9IP2 OC9IP1 OC9IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 IC9IP<2:0>: Input Capture Channel 9 Inter
PIC24FJ256GA110 FAMILY REGISTER 7-39: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Inter
PIC24FJ256GA110 FAMILY 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 114 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 8.0 • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • A separate and independently configurable system clock output for synchronizing external hardware OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of this group of PIC24F devices.
PIC24FJ256GA110 FAMILY 8.1 CPU Clocking Scheme 8.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The Primary Oscillator and FRC sources have the option of using the internal 4x PLL. The frequency of the FRC clock source can optionally be reduced by the programmable clock divider.
PIC24FJ256GA110 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): • OSCCON • CLKDIV • OSCTUN The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator. The OSCTUN register (Register 8-3) allows the user to fine tune the FRC Oscillator over a range of approximately ±12%. The OSCCON register (Register 8-1) is the main control register for the oscillator.
PIC24FJ256GA110 FAMILY REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24FJ256GA110 FAMILY REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-0 DOZE2 DOZE1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and
PIC24FJ256GA110 FAMILY REGISTER 8-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator T
PIC24FJ256GA110 FAMILY 8.4.2 OSCILLATOR SWITCHING SEQUENCE A recommended code sequence for a clock switch includes the following: At a minimum, performing a clock switch requires this basic sequence: 1. 1. 2. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON<14:12>) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source.
PIC24FJ256GA110 FAMILY 8.5 Reference Clock Output In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ256GA110 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application.
PIC24FJ256GA110 FAMILY REGISTER 8-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Referen
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 124 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 10. “Power-Saving Features” (DS39698). The PIC24FJ256GA110 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24FJ256GA110 FAMILY 9.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24FJ256GA110 FAMILY 10.0 Note: When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. I/O PORTS This data sheet summarizes the features of this group of PIC24F devices.
PIC24FJ256GA110 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
PIC24FJ256GA110 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GA110 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are disabled.
PIC24FJ256GA110 FAMILY 10.4.2 AVAILABLE PERIPHERALS The peripherals managed by the Peripheral Pin Select are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals.
PIC24FJ256GA110 FAMILY TABLE 10-2: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name Register Function Mapping Bits External Interrupt 1 INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> External Interrupt 3 INT3 RPINR1 INT3R<5:0> External Interrupt 4 Input Name INT4 RPINR2 INT4R<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Input Capture 3 IC3 RPINR8 IC3R<5:0> Input Capture 4 IC4 RPINR8 IC4R<5:0> Input C
PIC24FJ256GA110 FAMILY TABLE 10-3: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS 5 U2TX 6 Note 1: 2: 3: 4: (3) U2RTS (3) Output Name UART1 Request To Send UART2 Transmit UART2 Request To Send 7 SDO1 SPI1 Data Output 8 SCK1OUT(4) SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock O
PIC24FJ256GA110 FAMILY 10.4.3.4 Mapping Limitations 10.4.4.1 The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs.
PIC24FJ256GA110 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Select options introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state.
PIC24FJ256GA110 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ256GA110 family of devices implements a total of 37 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (21) • Output Remappable Peripheral Registers (16) REGISTER 10-1: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 10.4.4.1 “Control Register Lock” for a specific command sequence.
PIC24FJ256GA110 FAMILY REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R<5:0>: Assign E
PIC24FJ256GA110 FAMILY REGISTER 10-5: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ256GA110 FAMILY REGISTER 10-7: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ256GA110 FAMILY REGISTER 10-9: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘
PIC24FJ256GA110 FAMILY REGISTER 10-11: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC9R<5:0>: Assign Input
PIC24FJ256GA110 FAMILY REGISTER 10-13: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimple
PIC24FJ256GA110 FAMILY REGISTER 10-15: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GA110 FAMILY REGISTER 10-17: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GA110 FAMILY REGISTER 10-19: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimple
PIC24FJ256GA110 FAMILY REGISTER 10-21: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Sl
PIC24FJ256GA110 FAMILY REGISTER 10-22: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ256GA110 FAMILY REGISTER 10-24: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimpleme
PIC24FJ256GA110 FAMILY REGISTER 10-26: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
PIC24FJ256GA110 FAMILY REGISTER 10-28: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ256GA110 FAMILY REGISTER 10-30: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented:
PIC24FJ256GA110 FAMILY REGISTER 10-32: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GA110 FAMILY REGISTER 10-34: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GA110 FAMILY REGISTER 10-36: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented
PIC24FJ256GA110 FAMILY REGISTER 10-38: ALTRP: ALTERNATE PERIPHERAL PIN MAPPING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SCK1CM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 Unimplemented: Read as ‘0’ bit 0 SCK1CM: SCK1 Output Mapping Select bit 1 = SCK1 output function is mapped to
PIC24FJ256GA110 FAMILY 11.0 Note: Figure 11-1 presents a block diagram of the 16-bit timer module. TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3.
PIC24FJ256GA110 FAMILY REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Re
PIC24FJ256GA110 FAMILY 12.0 Note: TIMER2/3 AND TIMER4/5 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. 2. 3. 4.
PIC24FJ256GA110 FAMILY FIGURE 12-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK (T4CK) 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TGATE(2) TCS(2) Q 1 Set T3IF (T5IF) Q 0 PR3 (PR5) ADC Event Trigger(3) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 (1) Read TMR2 (TMR4) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counte
PIC24FJ256GA110 FAMILY FIGURE 12-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK (T4CK) TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS(1) TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TGATE(1) TMR2 (TMR4) Sync Comparator PR2 (PR4) The Timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information.
PIC24FJ256GA110 FAMILY REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-b
PIC24FJ256GA110 FAMILY REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timer
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 162 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 13.0 Note: INPUT CAPTURE WITH DEDICATED TIMER 13.1 13.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 34. “Input Capture with Dedicated Timer” (DS39722) Devices in the PIC24FJ256GA110 family all feature 9 independent enhanced input capture modules.
PIC24FJ256GA110 FAMILY 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd-numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (ICy) provides the Most Significant 16 bits.
PIC24FJ256GA110 FAMILY REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HCS R-0, HCS R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FJ256GA110 FAMILY REGISTER 13-2: U-0 — bit 15 R/W-0 ICTRIG bit 7 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0, HS TRIGSTAT U-0 — R/W-0 SYNCSEL4 R/W-1 SYNCSEL3 R/W-1 SYNCSEL2 R/W-0 SYNCSEL1 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7 bit 6 bit 5 bit 4-0 Note 1: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 R/W-0 IC32 bit 8 R/W-1 SYNCSEL0 bit 0 HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
PIC24FJ256GA110 FAMILY 14.0 Note: OUTPUT COMPARE WITH DEDICATED TIMER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 35. “Output Compare with Dedicated Timer” (DS39723) Devices in the PIC24FJ256GA110 family all feature 9 independent enhanced output compare modules.
PIC24FJ256GA110 FAMILY 14.2 3. Compare Operations In Compare mode (Figure 14-1), the enhanced output compare module can be configured for single-shot or continuous pulse generation; it can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. Configure the OCx output for one of the available Peripheral Pin Select pins.
PIC24FJ256GA110 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. 2. 3. 4. 5. 6. Set the OC32 bits for both registers (OCyCON2<8> and (OCxCON2<8>). Enable the even-numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2<7>), so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCyCON2. Force the output pin for OCx to the output state by clearing the OCTRIS bit.
PIC24FJ256GA110 FAMILY FIGURE 14-2: OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCxCON2 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxR Rollover/Reset OCxR Buffer OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin Clock Select OC Clock Sources Increment Comparator OCxTMR Reset Trigger and Sync Logic Trigger and Sync Sources Match Event Comparator Match Event Rollover OC Output and Fault Logic(1) OCFA/OCFB Match Event OCxRS buffer Rollover/Reset OCxRS
PIC24FJ256GA110 FAMILY CALCULATION FOR MAXIMUM PWM RESOLUTION(1) EQUATION 14-2: log10 Maximum PWM Resolution (bits) = (F PWM ) FCY • (Timer Prescale Value) bits log10(2) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. EXAMPLE 14-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.
PIC24FJ256GA110 FAMILY REGISTER 14-1: U-0 — bit 15 U-0 — ENFLT0 bit 7 Legend: R = Readable bit -n = Value at POR bit 12-10 bit 9-8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: 2: R/W-0 OCSIDL R/W-0 OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 U-0 — U-0 — bit 8 R/W-0 bit 15-14 bit 13 OCxCON1: OUTPUT COMPARE x CONTROL 1 REGISTER U-0 U-0 R/W-0, HCS — — OCFLT0 R/W-0 TRIGMODE R/W-0 OCM2(1) R/W-0 OCM1(1) R/W-0 OCM0(1) bit 0 HCS = Hardware Clearable/Settable bit W = Writable bit U = Unimplemented b
PIC24FJ256GA110 FAMILY REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL 2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleare
PIC24FJ256GA110 FAMILY REGISTER 14-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL 2 REGISTER (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 10
PIC24FJ256GA110 FAMILY 15.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699). The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices.
PIC24FJ256GA110 FAMILY To set up the SPI module for the Standard Master mode of operation: To set up the SPI module for the Standard Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with the MSTEN bit (SPIxCON1<5>) = 1.
PIC24FJ256GA110 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with the MSTEN bit (SPIxCON1<5>) = 1.
PIC24FJ256GA110 FAMILY REGISTER 15-1: R/W-0 SPIEN (1) SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 R/W-0 U-0 U-0 R-0 R-0 R-0 — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0 R/C-0, HS R-0 R/W-0 R/W-0 R/W-0 R-0 R-0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
PIC24FJ256GA110 FAMILY REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
PIC24FJ256GA110 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK(1) DISSDO(2) MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 (4) SSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘
PIC24FJ256GA110 FAMILY REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin (or to ASCK1 for SPI1).
PIC24FJ256GA110 FAMILY FIGURE 15-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDIx SDOx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) SDOx SDIx Shift Register (SPIxSR) LSb MSb MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF)(2) Shift Register (SPIxSR) LSb Serial Transmit Buffer (SPIxTXB) SCKx Serial Clock SCKx SPIx Buffer (SPIxBUF)(2) SSx(1) SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 MSTEN (SPIxCON1<5
PIC24FJ256GA110 FAMILY FIGURE 15-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Master, Frame Master) SDIx SDOx SDOx SDIx SCKx SSx FIGURE 15-6: Serial Clock Frame Sync Pulse SCKx SSx SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Master, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 15-7: Serial Clock Frame Sync Pulse SCKx SSx SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Master) SDOx SDIx SDIx SDOx SCK
PIC24FJ256GA110 FAMILY EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.
PIC24FJ256GA110 FAMILY 16.0 Note: INTER-INTEGRATED CIRCUIT (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit (I2C™)” (DS39702). The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices.
PIC24FJ256GA110 FAMILY FIGURE 16-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS39905E-page 186 2010 Microchip Technol
PIC24FJ256GA110 FAMILY 16.3 Setting Baud Rate When Operating as a Bus Master 16.4 The I2CxMSK register (Register 16-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘00010000’, the slave module will detect both addresses: ‘0000000’ and ‘0010000’.
PIC24FJ256GA110 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B
PIC24FJ256GA110 FAMILY REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.
PIC24FJ256GA110 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC IWCOL I2COV D/A P R-0, HSC R-0, HSC R-0, HSC R/W RBF TBF S bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC24FJ256GA110 FAMILY REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
PIC24FJ256GA110 FAMILY REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 A
PIC24FJ256GA110 FAMILY 17.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family.
PIC24FJ256GA110 FAMILY 17.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 17-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 17-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 17-2 shows the formula for computation of the baud rate with BRGH = 1.
PIC24FJ256GA110 FAMILY 17.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of UxTXREG word.
PIC24FJ256GA110 FAMILY REGISTER 17-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 (1) UARTEN — R/W-0 USIDL R/W-0 IREN (2) R/W-0 U-0 R/W-0 R/W-0 RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x
PIC24FJ256GA110 FAMILY REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (baud clock generated from FCY/4) 0 = Standard mode (baud clock generated from FCY/16) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bi
PIC24FJ256GA110 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV(1) UTXISEL0 — UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit i
PIC24FJ256GA110 FAMILY REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 200 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 18.0 Note: PARALLEL MASTER PORT (PMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 13. “Parallel Master Port (PMP)” (DS39713).
PIC24FJ256GA110 FAMILY REGISTER 18-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN:
PIC24FJ256GA110 FAMILY REGISTER 18-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master Mode 2 (PMMODE<9:8> = 00, 01, 10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master Mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Stro
PIC24FJ256GA110 FAMILY REGISTER 18-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC24FJ256GA110 FAMILY REGISTER 18-3: PMADDR: PARALLEL MASTER PORT ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CS2: Chip Select 2 bit 1 =
PIC24FJ256GA110 FAMILY REGISTER 18-5: PMSTAT: PARALLEL MASTER PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Statu
PIC24FJ256GA110 FAMILY REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — U-0 — — U-0 — U-0 — U-0 — R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clo
PIC24FJ256GA110 FAMILY FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMD<7:0> FIGURE 18-3: PMD<7:0> PMCS1 PMCS1 PMRD PMRD PMWR PMWR Address Bus Data Bus Control Lines ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMA<1:0> PMA<1:0> PMD<7:0> PMD<7:0> Read Address Decode PMDOUT1L (0) PMDIN1L (0) PMDOUT1H (1) PMDIN1H (1) PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMDOUT2H (3) PMDIN2H (3) PMCS1 PMCS1 PMRD PMWR Write Address Decode Address Bus Data Bus
PIC24FJ256GA110 FAMILY FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 Address Bus PMCS2 Multiplexed Data and Address Bus PMALL PMRD Control Lines PMWR FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F PMD<7:0> PMA<13:8> PMCS1 PMCS2 PMALL PMALH Multiplexed Data and Address Bus PMRD Control Lines PMWR FIGURE 18-7: EXAMPLE OF A
PIC24FJ256GA110 FAMILY FIGURE 18-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> A<7:0> 373 PMALL PMA<10:8> D<7:0> A<10:8> A<10:0> D<7:0> CE OE PMCS1 WR Data Bus PMRD Control Lines PMWR FIGURE 18-9: Address Bus EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F Parallel Peripheral PMD<7:0> PMALL AD<7:0> ALE PMCS1 CS Address Bus PMRD RD Data Bus PMWR WR Control Lines FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT
PIC24FJ256GA110 FAMILY 19.
PIC24FJ256GA110 FAMILY 19.1 TABLE 19-2: RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.1.1 To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 19-1).
PIC24FJ256GA110 FAMILY 19.1.
PIC24FJ256GA110 FAMILY REGISTER 19-1: bit 7-0 Note 1: 2: 3: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ...
PIC24FJ256GA110 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 AL
PIC24FJ256GA110 FAMILY 19.1.
PIC24FJ256GA110 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDA
PIC24FJ256GA110 FAMILY 19.1.
PIC24FJ256GA110 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimpl
PIC24FJ256GA110 FAMILY 19.3 After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 19-3) • One-time alarm and repeat alarm options available 19.3.1 Indefinite repetition of the alarm can occur if the CHIME bit = 1.
PIC24FJ256GA110 FAMILY 20.0 Note: Consider the CRC equation: PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR x16 + x12 + x5 + 1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 30. “Programmable Cyclic Redundancy Check (CRC)” (DS39714).
PIC24FJ256GA110 FAMILY FIGURE 20-2: CRC SHIFT ENGINE DETAIL CRCWDAT Read/Write Bus X(1)(1) Shift Buffer Data Note 1: 2: 20.1 20.1.1 Bit 0 X(2)(1) Bit 1 X(n)(1) Bit n(2) Bit 2 Each XOR stage of the shift engine is programmable. See text for details. Polynomial length n is determined by ([PLEN<3:0>] + 1). User Interface DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit.
PIC24FJ256GA110 FAMILY 20.
PIC24FJ256GA110 FAMILY REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘
PIC24FJ256GA110 FAMILY 21.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is shown in Figure 21-1. To perform an A/D conversion: 1.
PIC24FJ256GA110 FAMILY FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD VR+ 16 VR- VREF- Comparator VINH AN0 VINL VRS/H VR+ DAC AN1 AN2 AN5 MUX A AN4 10-Bit SAR VINH AN3 Conversion Logic Data Formatting AN6 VINL AN7 ADC1BUF0: ADC1BUFF AN8 AD1CON1 AD1CON2 AD1CON3 AN9 AN10 AD1CHS AN12 AN13 AN14 MUX B AN11 VINH AD1PCFGL AD1PCFGH AD1CSSL VINL AN15 VBG VBG/2 DS39905E-page 226 Sample Control Control Logic Conversion Contro
PIC24FJ256GA110 FAMILY REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R-0, HCS SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/
PIC24FJ256GA110 FAMILY REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r — CSCNA — — bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Voltage Reference Conf
PIC24FJ256GA110 FAMILY REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source
PIC24FJ256GA110 FAMILY REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB — — CH0SB4(1) CH0SB3(1) CH0SB2(1) CH0SB1(1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0
PIC24FJ256GA110 FAMILY REGISTER 21-5: AD1PCFGL: A/D PORT CONFIGURATION REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unkno
PIC24FJ256GA110 FAMILY REGISTER 21-7: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown
PIC24FJ256GA110 FAMILY A/D CONVERSION CLOCK PERIOD(1) EQUATION 21-1: TAD = TCY • (ADCS + 1) ADCS = Note 1: FIGURE 21-2: TAD –1 TCY Based on TCY = 2 * TOSC, Doze mode and PLL are disabled. 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC 250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS 5 k(Typical) RSS ILEAKAGE 500 nA CHOLD = DAC capacitance = 4.
PIC24FJ256GA110 FAMILY FIGURE 21-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) DS39905E-page 234 (VINH – VINL) VR+ 1024 1023*(VR+ – VR-) VR- + 1024 VR- + 512*(VR+ – VR-) 1024 VR- + Voltage Level VR+ – VR- 0 VR- 00 0000 0000 (0) 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 22.0 The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. TRIPLE COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 19. “Comparator Module” (DS39710).
PIC24FJ256GA110 FAMILY FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CEN = 0, CREF = x, CCH<1:0> = xx COE VINVIN+ Cx Off (Read as ‘0’) Comparator CxINB > CxINA Compare CEN = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN+ Comparator CxINC > CxINA Compare CEN = 1, CREF = 0, CCH<1:0> = 01 COE VIN- CXINC Cx CxOUT Pin CXINA COE VINVIN+ VBG/2 Cx CxOUT Pin Comparator CxINB > CVREF Compare CEN = 1, CREF = 1, CCH<1:0> = 00 CXINB CVREF CXINC Cx CxOUT Pin CVREF DS39905E-page 236
PIC24FJ256GA110 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0 CEN COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CEN: Comparator Enable bit 1 = Co
PIC24FJ256GA110 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CXINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CXIND pin 01 = Inverting input of
PIC24FJ256GA110 FAMILY 23.0 Note: 23.1 voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR<3:0>), with one range offering finer resolution. COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24FJ256GA110 FAMILY REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Compara
PIC24FJ256GA110 FAMILY 24.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) 24.1 The CTMU module measures capacitance by generating an output pulse, with a width equal to the time, between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2).
PIC24FJ256GA110 FAMILY 24.2 When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected.
PIC24FJ256GA110 FAMILY REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Ena
PIC24FJ256GA110 FAMILY REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred Note 1: If TGEN = 1, the CTEDGx inputs and CTPLS outputs must be assigned to available RPn pins before use.
PIC24FJ256GA110 FAMILY 25.0 Note: 25.1.1 SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33.
PIC24FJ256GA110 FAMILY REGISTER 25-1: CW1: FLASH CONFIGURATION WORD 1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 r JTAGEN GCP GWRP DEBUG r ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program Once bit -n = Value when
PIC24FJ256GA110 FAMILY REGISTER 25-1: bit 3-0 CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY REGISTER 25-2: CW2: FLASH CONFIGURATION WORD 2 R/PO-1 — bit 23 R/PO-1 — R/PO-1 — R/PO-1 — R/PO-1 — R/PO-1 — R/PO-1 — R/PO-1 — bit 16 R/PO-1 IESO bit 15 R/PO-1 — R/PO-1 — R/PO-1 — R/PO-1 — R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FNOSC0 bit 8 R/PO-1 FCKSM1 bit 7 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY R/PO-1 — R/PO-1 I2C2SEL(1) R/PO-1 POSCMD1 R/PO-1 POSCMD0 bit 0 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit
PIC24FJ256GA110 FAMILY REGISTER 25-2: bit 1-0 Note 1: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected Implemented in 100-pin devices only; otherwise unimplemented, read as ‘1’.
PIC24FJ256GA110 FAMILY REGISTER 25-4: DEVID: DEVICE ID REGISTER U — bit 23 U — U — U — U — U — U — U — bit 15 U — R FAMID7 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 bit 8 R FAMID0 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID1 bit 7 Legend: R = Read-Only bit bit 23-14 bit 13-6 bit 5-0 U — bit 16 U = Unimplemented bit Unimplemented: Read as ‘1’ FAMID<7:0>: Device Family Identifier bits 01000000 = PIC24FJ256GA110 family DEV<5:0>: Individual Device Identifier bits 00000
PIC24FJ256GA110 FAMILY 25.2 On-Chip Voltage Regulator All PIC24FJ256GA110 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GA110 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin.
PIC24FJ256GA110 FAMILY 25.2.2 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TVREG, code execution is disabled. TVREG is applied every time the device resumes operation after any power-down, including Sleep mode. The length of TVREG is determined by the PMSLP bit (RCON<8>), as described in Section 25.2.5 “Voltage Regulator Standby Mode”.
PIC24FJ256GA110 FAMILY 25.3.1 WINDOWED OPERATION 25.3.2 The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1<6>) to ‘0’.
PIC24FJ256GA110 FAMILY 25.4.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of erase and write-protected code is needed, such as bootloader applications.
PIC24FJ256GA110 FAMILY 25.5 JTAG Interface PIC24FJ256GA110 family devices implement a JTAG interface, which supports boundary scan device testing. 25.6 In-Circuit Serial Programming PIC24FJ256GA110 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power, ground and the programming voltage.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 256 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 26.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24FJ256GA110 FAMILY TABLE 26-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24FJ256GA110 FAMILY TABLE 26-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C,
PIC24FJ256GA110 FAMILY TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24FJ256GA110 FAMILY TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 W
PIC24FJ256GA110 FAMILY TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 No
PIC24FJ256GA110 FAMILY TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 264 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 27.
PIC24FJ256GA110 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC24FJ256GA110 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24FJ256GA110 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24FJ256GA110 FAMILY 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256GA110 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GA110 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24FJ256GA110 FAMILY 28.1 DC Characteristics FIGURE 28-1: PIC24FJ256GA110 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.00V Voltage (VDDCORE)(1) 2.75V 2.75V 2.50V PIC24FJXXXGA1XX 2.25V 2.25V 2.00V 32 MHz 16 MHz Frequency For frequencies between 16 MHz and 32 MHz, FMAX = (64 MHz/V) * (VDDCORE – 2V) + 16 MHz. When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V.
PIC24FJ256GA110 FAMILY TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ(1) Max Units VDD VBOR — 3.6 V Regulator enabled VDD VDDCORE — 3.6 V Regulator disabled Regulator disabled Characteristic Conditions Operating Voltage DC10 Supply Voltage 2.0 — 2.
PIC24FJ256GA110 FAMILY FIGURE 28-2: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR SY12 SY10 Internal POR PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins DS39905E-page 272 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD): PMD Bits are Set(2) DC20 0.83 1.2 mA -40°C DC20a 0.83 1.2 mA +25°C DC20b 0.83 1.2 mA +85°C DC20c 0.9 1.3 mA +125°C DC20d 1.1 1.7 mA -40°C DC20e 1.1 1.
PIC24FJ256GA110 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
PIC24FJ256GA110 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2) DC51 4.3 13.0 A -40°C DC51a 4.5 13.
PIC24FJ256GA110 FAMILY TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC60 0.1 1.0 A -40°C DC60a 0.15 1.0 A +25°C DC60m 2.25 11 A +60°C DC60b 3.7 18.0 A +85°C DC60j 18.0 85.
PIC24FJ256GA110 FAMILY TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC62 2.5 7.0 A -40°C DC62a 2.5 7.0 A +25°C DC62m 3.0 7.0 A +60°C DC62b 3.0 7.
PIC24FJ256GA110 FAMILY TABLE 28-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Sym No. VIL DI10 Characteristic Min Typ(1) Max Units VSS — 0.2 VDD V Input Low Voltage(4) I/O Pins with ST Buffer DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSC1 (XT mode) VSS — 0.
PIC24FJ256GA110 FAMILY TABLE 28-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param Sym No. Characteristic Standard Operating Conditions: 2.0V to 3.
PIC24FJ256GA110 FAMILY TABLE 28-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Min Typ(1) Max 10000 — — VMIN — 3.6 V VDDCORE 2.25 — VDDCORE V VDD 2.35 — 3.
PIC24FJ256GA110 FAMILY FIGURE 28-3: CTMU CURRENT SOURCE CALIBRATION CIRCUIT PIC24F Device Current Source CTMU A/D Trigger A/D Converter AN2 RCAL 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 28.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256GA110 family AC characteristics and timing parameters. TABLE 28-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 28.1 “DC Characteristics”.
PIC24FJ256GA110 FAMILY FIGURE 28-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS31 OS30 OS31 OS25 CLKO OS40 OS41 TABLE 28-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (external clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.50 to 3.
PIC24FJ256GA110 FAMILY TABLE 28-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) AC CHARACTERISTICS Param No. Characteristic(1) Sym Standard Operating Conditions: 2.0V to 3.
PIC24FJ256GA110 FAMILY FIGURE 28-6: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 28-4 for load conditions. TABLE 28-17: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY TABLE 28-19: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.
PIC24FJ256GA110 FAMILY TABLE 28-20: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
PIC24FJ256GA110 FAMILY FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR SY12 SY10 Internal POR PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins TABLE 28-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.
PIC24FJ256GA110 FAMILY FIGURE 28-8: BAUD RATE GENERATOR OUTPUT TIMING BRGx + 1 * TCY TLW THW BCLKx TBLD TBHD UxTX FIGURE 28-9: START BIT EDGE DETECTION BRGx Any Value Start bit Detected, BRGx Started TCY Cycle Clock TSETUP TSTDELAY UxRX TABLE 28-22: AC SPECIFICATIONS Symbol Characteristics Min Typ Max Units TLW BCLKx High Time 20 TCY/2 — ns THW BCLKx Low Time 20 (TCY * BRGx) + TCY/2 — ns TBLD BCLKx Falling Edge Delay from UxTX -50 — 50 ns TBHD BCLKx Rising Edge Delay from
PIC24FJ256GA110 FAMILY FIGURE 28-10: INPUT CAPTURE TIMINGS ICx pin (Input Capture Mode) IC11 IC10 IC15 TABLE 28-23: INPUT CAPTURE Param. Symbol No.
PIC24FJ256GA110 FAMILY FIGURE 28-11: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0) SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 TABLE 28-24: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY FIGURE 28-12: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1) SP36 SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 Bit 14 - - - - - -1 MSb SDOx SP40 SDIx LSb SP30,SP31 Bit 14 - - - -1 MSb In LSb In SP41 TABLE 28-25: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY FIGURE 28-13: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0) SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 28-26: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY FIGURE 28-14: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1) SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIx MSb In LSb In Bit 14 - - - -1 SP41 SP40 TABLE 28-27: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.
PIC24FJ256GA110 FAMILY FIGURE 28-15: OUTPUT COMPARE TIMINGS OCx (Output Compare or PWM Mode) OC11 TABLE 28-28: OUTPUT COMPARE Param. No. Symbol OC11 TCCR OC10 TCCF FIGURE 28-16: OC10 Characteristic OC1 Output Rise Time OC1 Output Fall Time Min Max Unit Condition — 10 ns — — — ns — — 10 ns — — — ns — PWM MODULE TIMING REQUIREMENTS OC20 OCFx OC15 PWM TABLE 28-29: PWM TIMING REQUIREMENTS Param. Symbol No.
PIC24FJ256GA110 FAMILY I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) FIGURE 28-17: SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 28-4 for load conditions. TABLE 28-30: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) AC CHARACTERISTICS Param Symbol No.
PIC24FJ256GA110 FAMILY FIGURE 28-18: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 SCLx SDAx In IM21 IM10 IM26 IM20 IM25 IM45 IM40 SDAx Out Note: Refer to Figure 28-4 for load conditions. TABLE 28-31: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) FIGURE 28-19: SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition TABLE 28-32: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY FIGURE 28-20: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out TABLE 28-33: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) AC CHARACTERISTICS Param No.
PIC24FJ256GA110 FAMILY FIGURE 28-21: PARALLEL SLAVE PORT TIMING CS RD WR PS4 PMD<7:0> PS1 PS3 PS2 TABLE 28-34: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial AC CHARACTERISTICS Param. No.
PIC24FJ256GA110 FAMILY FIGURE 28-22: PARALLEL MASTER PORT READ TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock Address PMA<13:18> Address<7:0> PMD<7:0> Data PM6 PM2 PM7 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS<2:1> Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-35: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.
PIC24FJ256GA110 FAMILY FIGURE 28-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA<13:18> Address Address<7:0> PMD<7:0> Data PM13 PM12 PMRD PMWR PM11 PMALL/PMALH PMCS<2:1> PM16 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-36: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.
PIC24FJ256GA110 FAMILY TABLE 28-37: COMPARATOR TIMINGS Param Symbol No. Characteristic Typ Max Units — 150 400 ns — — 10 s Response Time*(1) 300 TRESP 301 TMC2OV Comparator Mode Chance to Output Valid* * Note 1: Min Comments Parameters are characterized but not tested. Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 28-38: DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 304 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC24FJ256 GA106-I/ PT e3 1020017 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 80-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC24FJ256GA110 FAMILY 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN DS39905E-page 306 Example PIC24FJ256GA 110-I/PT e3 0920017 Example PIC24FJ256GA 110-I/PF e3 0920017 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY 29.2 Package Details The following sections give the technical details of the packages.
PIC24FJ256GA110 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 DS39905E-page 308 # * !( 4 ! ! & 4 % & & # & 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39905E-page 310 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY ) ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c φ β A2 A1 L1 L 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : @ / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4 4
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PIC24FJ256GA110 FAMILY ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 77 . .
PIC24FJ256GA110 FAMILY ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4
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PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 318 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY APPENDIX A: REVISION HISTORY Revision A (December 2007) Original data sheet for the PIC24FJ256GA110 family of devices. Revision B (February 2008) Updates to Section 28.0 “Electrical Characteristics” and minor edits to text throughout document. Revision C (April 2009) Updates to all Pin Diagrams to reflect the correct order of priority for multiplexed peripherals and adds the ASCK1 pin function. Adds packaging information for the new 64-pin QFN package to Section 29.
PIC24FJ256GA110 FAMILY Revision E (November 2010) Added 64-Kbyte device variants – PIC24FJ64GA106, PIC24FJ64GA108 and PIC24FJ64GA110. Changed the CON bit to CEN to match other existing PIC24F, PIC24H and dsPIC® products. Changed the VREFS bit to PMSLP to match other existing PIC24F, PIC24H and dsPIC® products. Corrected the OCxCON2 and ICxCON2 Reset values in the register descriptions. Defined SOSC and RTCC behavior during MCLR events. Corrected the RCFGCAL Reset values in the register descriptions.
PIC24FJ256GA110 FAMILY INDEX Reset System ............................................................ 65 RTCC ....................................................................... 211 Shared I/O Port Structure ........................................ 127 SPI Master, Frame Master Connection ................... 183 SPI Master, Frame Slave Connection ..................... 183 SPI Master/Slave Connection (Enhanced Buffer Modes) ................................
PIC24FJ256GA110 FAMILY CTMU Measuring Capacitance ........................................... 241 Measuring Time ....................................................... 242 Pulse Generation and Delay .................................... 242 Customer Change Notification Service ............................ 326 Customer Notification Service .......................................... 326 Customer Support ............................................................ 326 D Data Memory Address Space .............
PIC24FJ256GA110 FAMILY Output Compare Cascaded (32-Bit) Mode .......................................... 167 Operations ............................................................... 168 Synchronous and Trigger Modes ............................. 167 Output Compare with Dedicated Timer ............................ 167 P Packaging ........................................................................ 305 Details ...................................................................... 307 Marking ...........
PIC24FJ256GA110 FAMILY IPC12 (Interrupt Priority Control 12) ........................ 103 IPC13 (Interrupt Priority Control 13) ........................ 104 IPC15 (Interrupt Priority Control 15) ........................ 105 IPC16 (Interrupt Priority Control 16) ........................ 106 IPC18 (Interrupt Priority Control 18) ........................ 107 IPC19 (Interrupt Priority Control 19) ........................ 107 IPC2 (Interrupt Priority Control 2) ..............................
PIC24FJ256GA110 FAMILY Timing Requirements Comparator .............................................................. 303 DC ............................................................................ 303 I2C Bus Data (Master Mode) ............................ 296, 297 I2C Bus Data (Slave Mode) ...................................... 299 I2C Bus Start/Stop Bit (Slave Mode) ........................ 298 Input Capture ........................................................... 290 Output Compare ...............
PIC24FJ256GA110 FAMILY NOTES: DS39905E-page 326 2010 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24FJ256GA110 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24FJ256GA110 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GA1 10 T - I / PT - XXX Examples: a) Microchip Trademark Architecture b) Flash Memory Family Program Memory Size (KB) PIC24FJ128GA106-I/PT: General purpose PIC24F, 128-Kbyte program memory, 64-pin, Industrial temp.,TQFP package. PIC24FJ256GA110-I/PT: General purpose PIC24F, 256-Kbyte program memory, 100-pin, Industrial temp.
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