Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 64 Exposed Pad (9x9) 16-Bit 32 MHz I/O number 53

 2008-2013 Microchip Technology Inc. DS80368N-page 1

PIC24FJ256GA110 FAMILY

The PIC24FJ256GA110 family devices that you have

received conform functionally to the current Device Data

Sheet (DS39905E), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1 . The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC24FJ256GA110 family

silicon.

Data Sheet clarifications and corrections start on page 12,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2

programmer/debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various

PIC24FJ256GA110 family silicon revisions are

shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A6).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number

Device

(1)

Revision ID for

Silicon Revision

(2)

Part Number

Device

(1)

Revision ID for

Silicon Revision

(2)

A3 A5 A6 A3 A5 A6

PIC24FJ256GA110 101Eh

01h 03h 04h

PIC24FJ128GA108 100Ah

01h 03h 04h

PIC24FJ192GA110 1016h PIC24FJ64GA108 1002h

PIC24FJ128GA110 100Eh PIC24FJ256GA106 1018h

PIC24FJ64GA110 1006h PIC24FJ192GA106 1010h

PIC24FJ256GA108 101Ah PIC24FJ128GA106 1008h

PIC24FJ192GA108 1012h PIC24FJ64GA106 1000h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC24FJXXXGA0XX Flash Programming Specification” (DS39768) for detailed information

on Device and Revision IDs for your specific device.

PIC24FJ256GA110 Family

Silicon Errata and Data Sheet Clarification

Summary of content (22 pages)

PAGE 1
PIC24FJ256GA110 FAMILY PIC24FJ256GA110 Family Silicon Errata and Data Sheet Clarification The PIC24FJ256GA110 family devices that you have received conform functionally to the current Device Data Sheet (DS39905E), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC24FJ256GA110 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A3 A5 A6 X X X X X X Core RAM Operation 1. RAM issues in Doze mode. X Core BOR 2. BOR issues in enabled on-chip regulator. X JTAG Device  Programming 3. JTAG issues in device programming. X 4. Framing errors in UART. X UART — I/O PORTB 5. RB5 issues in open-drain operation. X SPI Master mode 6. Early one-half clock cycles. X 7.
PAGE 3
PIC24FJ256GA110 FAMILY TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Feature Item Number CTMU — 29. Oscillator — Module Issue Summary Affected Revisions(1) A3 A5 A6 Disabling module affects band gap. X X X 30. POSCEN bit does not work with  Primary + PLL modes. X X X Output  Compare Interrupt 31. Interrupt flag may precede the output pin change under certain circumstances. X X X UART Transmit 32. A TX interrupt may occur before the data transmission is complete.
PAGE 4
PIC24FJ256GA110 FAMILY Silicon Errata Issues Note: 3. Module: JTAG (Device Programming) The JTAGEN Configuration bit can be programmed to ‘0’ while using the JTAG interface for device programming. This may cause a situation where JTAG programming can lock itself out of being able to program the device. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.
PAGE 5
PIC24FJ256GA110 FAMILY 6. Module: SPIx (Master Mode) 7. Module: CTMU In Master mode, both the SPIx Interrupt Flag (SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may become set one-half clock cycle early, instead of on the clock edge.
PAGE 6
PIC24FJ256GA110 FAMILY 8. Module: UART (UxERIF Interrupt) The UART error interrupt may not occur, or occur at an incorrect time, if multiple errors occur during a short period of time. Work around Read the error flags in the UxSTA register whenever a byte is received to verify the error status. In most cases, these bits will be correct, even if the UART error interrupt fails to occur. For possible exceptions, refer to Errata # 9. Affected Silicon Revisions A3 A5 A6 X 9.
PAGE 7
PIC24FJ256GA110 FAMILY 14. Module: Core (Instruction Set) If an instruction producing a read-after-write stall condition is executed inside a REPEAT loop, the instruction will be executed fewer times than was intended. For example, this loop: repeat #0xf inc [w1],[++w1] will execute less than 15 times. Work around 16. Module: ICSP™ The ICSP/ICD port pair, PGEC3/PGED3 (RB5/RB4), cannot be used to read or program the device. Work around Use either PGEC2/PGED2 or PGEC1/PGED1.
PAGE 8
PIC24FJ256GA110 FAMILY 18. Module: I2C™ Module (Master Mode) Under certain circumstances, a module operating in Master mode may Acknowledge its own command addressed to a slave device. This happens when the following occurs: • 10-Bit Addressing mode is used (A10M = 1), and: • the I2C master has the same two upper address bits (I2CADD<9:8>) as the addressed slave module. 20.
PAGE 9
PIC24FJ256GA110 FAMILY 22. Module: Core (Code Protection) When General Segment Code Protection has been enabled (GCP Configuration bit is programmed), applications are unable to write to the first 512 bytes of the program memory space (0000h through 0200h). In applications that may require the interrupt vectors to be changed during run time, such as bootloaders, modifications to the interrupt vector tables will not be possible.
PAGE 10
PIC24FJ256GA110 FAMILY 27. Module: Interrupts (INTx) Writing to the INTCON2 register may cause an external interrupt event (inputs on INT0 through INT4) to be missed. This only happens when the interrupt event and the write event occur during the same clock cycle. Work around If possible, do not write to INTCON2 while any of the external interrupts are enabled.
PAGE 11
PIC24FJ256GA110 FAMILY 31. Module: Output Compare (Interrupt) Under certain circumstances, an output compare match may cause the interrupt flag (OCxIF) to become set prior to the Change-of-State (COS) of the OCx pin. This has been observed when all of the following are true: • the module is in One-Shot mode (OCM<2:0> = 001, 010 or 100); one of the timer modules is being used as the time base; and a timer prescaler other than 1:1 is selected.
PAGE 12
PIC24FJ256GA110 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39905E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. 1. Module: Guidelines for Getting Started with 16-Bit Microcontrollers Section 2.
PAGE 13
PIC24FJ256GA110 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PAGE 14
PIC24FJ256GA110 FAMILY 2. Module: Electrical Specifications 3. Module: Electrical Specifications In Table 28-3 (Temperature and Voltage Specifications), the Minimum value for BO10 (Brown-out Reset Voltage) is changed to 1.80V. Typical and Maximum values remain unchanged.
PAGE 15
PIC24FJ256GA110 FAMILY 4. Module: Electrical Specifications Tables 28-10 and 28-11 (shown below) are added to Section 28.0 “Electrical Characteristics”, following the existing Table 28-9 (Program Memory). All subsequent tables in the section are renumbered accordingly. (Bold text in these tables represents original and unmodified content.) TABLE 28-10: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No.
PAGE 16
PIC24FJ256GA110 FAMILY 5. Module: Electrical Specifications 6. Module: Electrical Specifications In Section 28.0 “Electrical Characteristics”, under Absolute Maximum Ratings on Page 269, the “Ambient temperature under bias” has been changed to -40°C to +135°C. TABLE 3: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL DO10 Characteristic I/O Ports VOH DO20 Min Typ(1) Max Units Conditions — — 0.4 V IOL = 8.5 mA, VDD = 3.6V — — 0.4 V IOL = 5.
PAGE 17
PIC24FJ256GA110 FAMILY 7. Module: Electrical Specifications In Section 28.0 “Electrical Characteristics”, Table 28-13 (External Clock Timing Requirements) has been replaced with Table 4 below: TABLE 4: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (External clocks allowed  only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.50 to 3.
PAGE 18
PIC24FJ256GA110 FAMILY 8. Module: Electrical Specifications In Section 28.0 “Electrical Characteristics”, Table 28-16 (Internal RC Oscillator Accuracy) is amended by the addition of the extended temperature condition to Parameter F20. (Bold text in this table represents the modified content; bold in existing text has been removed for clarity.) TABLE 28-16: INTERNAL RC OSCILLATOR ACCURACY AC CHARACTERISTICS Param No. F20 Characteristic FRC Accuracy @ 8 MHz(1) Standard Operating Conditions: 2.0V to 3.
PAGE 19
PIC24FJ256GA110 FAMILY 9. Module: Product Identification System The “Product Identification System” section on Page 329 has been amended by an additional temperature range. (Bold text in this section represents the modified content; bold in existing text has been removed for clarity.) PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PAGE 20
PIC24FJ256GA110 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (2/2008) Rev L Document (11/2011) Added silicon issues 29 (CTMU), 30 (Oscillator), 31 (Output Compare – Interrupt) and 32 (UART) to all current silicon revisions. First revision of this document. Includes silicon issues 1 (Core, RAM Operation), 2 (Core, BOR), 3 (JTAG, Programming), 4 (UART), 5 (I/O, PORTB), 6 (SPI) and 7 (Input Capture). Added data sheet clarifications 2, 3 and 4 (Electrical Specifications).
PAGE 21
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 22
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