Datasheet

PIC24FJ256DA210 FAMILY DS39969B-page 62  2010 Microchip Technology Inc.
AD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000
AD1CON2 0322 VCFG2 VCFG1 VCFG0
r — CSCNA — — BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000
AD1CON3 0324 ADRC
r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
AD1CHS 0328 CH0NB
— — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000
AD1CSSH 032E
— — — — CSSL27 CSSL26 CSSL25 CSSL24 CSSL23
(1)
CSSL22
(1)
CSSL21
(1)
CSSL20
(1)
CSSL19
(1)
CSSL18
(1)
CSSL17
(1)
CSSL16
(1)
0000
AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
TABLE 4-21: ADC REGISTER MAP (CONTINUED)
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
Legend: — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal.
Note 1: Unimplemented in 64-pin devices, read as ‘0’
TABLE 4-22: CTMU REGISTER MAP
File
Name
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
CTMUCON 033C CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000
CTMUICON 033E ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
— — — — — — — — 0000
Legend: — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.