Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 400  2010 Microchip Technology Inc.
CTMU
Measuring Capacitance ............................................343
Measuring Time ........................................................344
Pulse Delay and Generation ..................................... 344
Customer Change Notification Service ............................. 405
Customer Notification Service........................................... 405
Customer Support ............................................................. 405
D
Data Memory
Address Space............................................................ 47
Memory Map ............................................................... 48
Near Data Space ........................................................ 49
SFR Space.................................................................. 49
Software Stack............................................................75
Space Organization, Alignment .................................. 49
DC Characteristics
I/O Pin Input Specifications....................................... 377
I/O Pin Output Specifications ....................................378
Program Memory ...................................................... 378
Development Support ....................................................... 359
Device Features
100/121--Pin ............................................................... 19
64-Pin..........................................................................18
Doze Mode........................................................................ 156
E
EDS...................................................................................273
Electrical Characteristics
A/D Specifications.....................................................384
Absolute Maximum Ratings ...................................... 371
Capacitive Loading on Output Pin ............................380
External Clock Timing ...............................................381
Idle Current ............................................................... 375
Load Conditions and Requirements for
Specifications.................................................... 379
Operating Current ..................................................... 374
PLL Clock Timing Specifications............................... 381
Power-Down Current ................................................ 376
RC Oscillator Start-up Time ...................................... 382
Reset and Brown-out Reset Requirements .............. 382
Temperature and Voltage Specifications .................. 373
Thermal Conditions...................................................372
V/F Graph ................................................................. 372
Voltage Regulator Specifications ..............................379
Enhanced Parallel Master Port. See EPMP...................... 273
ENVREG Pin..................................................................... 354
EPMP................................................................................ 273
Alternative Master .....................................................273
Key Features.............................................................273
Master Port Pins ....................................................... 274
Equations
16-Bit, 32-Bit CRC Polynomials ................................ 298
A/D Conversion Clock Period ................................... 332
Baud Rate Reload Calculation.................................. 225
Calculating the PWM Period ..................................... 204
Calculation for Maximum PWM Resolution............... 205
Estimating USB Transceiver Current
Consumption..................................................... 243
Relationship Between Device and SPI
Clock Speed...................................................... 221
RTCC Calibration......................................................294
UART Baud Rate with BRGH = 0 ............................. 232
UART Baud Rate with BRGH = 1 ............................. 232
Errata .................................................................................. 14
F
Flash Configuration Words ......................................... 46, 347
Flash Program Memory ...................................................... 81
and Table Instructions ................................................ 81
Enhanced ICSP Operation ......................................... 82
JTAG Operation.......................................................... 82
Programming Algorithm .............................................. 84
RTSP Operation ......................................................... 82
Single-Word Programming ......................................... 86
G
Graphics Controller (GFX) ................................................ 305
Key Features ............................................................ 305
Graphics Controller Module (GFX) ................................... 305
Graphics Display Module
Display Clock (GCLK) Source .................................. 324
Display Configuration................................................ 324
Memory Locations .................................................... 324
Memory Requirements ............................................. 324
Module Registers...................................................... 306
Graphics Display Module (GFX) ....................................... 305
I
I/O Ports
Analog Port Pins Configuration................................. 158
Analog/Digital Function of an I/O Pin........................ 158
Input Change Notification ......................................... 163
Open-Drain Configuration......................................... 158
Parallel (PIO) ............................................................ 157
Peripheral Pin Select ................................................ 164
Pull-ups and Pull-downs ........................................... 163
Selectable Input Sources.......................................... 165
I
2
C
Clock Rates .............................................................. 225
Reserved Addresses ................................................ 225
Setting Baud Rate as Bus Master............................. 225
Slave Address Masking ............................................ 225
Idle Mode .......................................................................... 156
Input Capture
32-Bit Mode .............................................................. 198
Operations ................................................................ 198
Synchronous and Trigger Modes.............................. 197
Input Capture with Dedicated Timers ............................... 197
Input Voltage Levels for Port or Pin
Tolerated Description Input....................................... 158
Instruction Set
Overview................................................................... 365
Summary .................................................................. 363
Instruction-Based Power-Saving Modes................... 155, 156
Interfacing Program and Data Spaces................................ 75
Inter-Integrated Circuit. See I
2
C. ...................................... 223
Internet Address ............................................................... 405
Interrupt Vector Table (IVT) ................................................ 93
Interrupts
Control and Status Registers...................................... 96
Implemented Vectors.................................................. 95
Reset Sequence ......................................................... 93
Setup and Service Procedures................................. 140
Trap Vectors ............................................................... 94
Vector Table ............................................................... 94
J
JTAG Interface.................................................................. 358