Datasheet

 2010 Microchip Technology Inc. DS39969B-page 351
PIC24FJ256DA210 FAMILY
bit 4 IOL1WAY: IOLOCK One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been
completed. Once set, the Peripheral Pin Select registers cannot be written to a second time.
0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been
completed
bit 3-2 Reserved: Always maintain as ‘1’
bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits
11 = Primary oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
REGISTER 27-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)
REGISTER 27-3: CW3: FLASH CONFIGURATION WORD 3
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
WPEND WPCFG WPDIS ALTPMP
(1)
WUTSEL1 WUTSEL0 SOSCSEL1 SOSCSEL0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
WPFP7 WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0
bit 7 bit 0
Legend: PO = Program-Once bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘1’
bit 15 WPEND: Segment Write Protection End Page Select bit
1 = Protected code segment upper boundary is at the last page of program memory; the lower
boundary is the code page specified by WPFP<7:0>
0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper
boundary is the code page specified by WPFP<7:0>
bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit
1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected
(3)
0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = ‘0’
bit 13 WPDIS: Segment Write Protection Disable bit
1 = Segmented code protection is disabled
0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and
WPFPx Configuration bits
bit 12
ALTPMP:
Alternate EPMP Pin Mapping bit
(1)
1 = EPMP pins are in default location mode
0 = EPMP pins are in alternate location mode
Note 1: Unimplemented in 64-pin devices, maintain at ‘1’.
2: Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1.
3: Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page,
the Configuration Word’s page is protected.