Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 348  2010 Microchip Technology Inc.
REGISTER 27-1: CW1: FLASH CONFIGURATION WORD 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1
reserved JTAGEN GCP GWRP DEBUG reserved ICS1 ICS0
bit 15 bit 8
R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1
FWDTEN WINDIS ALTVREF
(1)
FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23-16 Unimplemented: Read as ‘1’
bit 15 Reserved: The value is unknown; program as ‘0’
bit 14 JTAGEN: JTAG Port Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
bit 13 GCP: General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
bit 12 GWRP: General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are not allowed
bit 11
DEBUG
: Background Debugger Enable bit
1 = Device resets into Operational mode
0 = Device resets into Debug mode
bit 10 Reserved: Always maintain as ‘1’
bit 9-8 ICS<1:0>: Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
10 = Emulator functions are shared with PGEC2/PGED2
01 = Emulator functions are shared with PGEC3/PGED3
00 = Reserved; do not use
bit 7 FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled
0 = Watchdog Timer is disabled
bit 6 WINDIS: Windowed Watchdog Timer Disable bit
1 = Standard Watchdog Timer is enabled
0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’
bit 5
ALTVREF
: Alternate VREF Pin Selection bit
(1)
1 =VREF is on a default pin (VREF+ on RA10 and VREF- on RA9)
0 =V
REF is on an alternate pin (VREF+ on RB0 and VREF- on RB1)
Note 1: Unimplemented in 64-pin devices, maintain at ‘1’ (V
REF+ on RB0 and VREF- on RB1).