Datasheet

 2010 Microchip Technology Inc. DS39969B-page 331
PIC24FJ256DA210 FAMILY
REGISTER 23-5: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — VBG6EN VBG2EN VBGEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2 VBG6EN: A/D Input V
BG/6 Enable bit
1 = Band gap voltage divided-by-six reference (V
BG/6) is enabled
0 = Band gap divided-by-six reference (V
BG/6) is disabled
bit 1 VBG2EN: A/D Input VBG/2 Enable bit
1 = Band gap voltage divided-by-two reference (VBG/2) is enabled
0 = Band gap divided-by-two reference (V
BG/2) is disabled
bit 0 VBGEN: A/D Input VBG Enable bit
1 = Band gap voltage reference (VBG) is enabled
0 = Band gap reference (V
BG) is disabled
REGISTER 23-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
bit 15 bit 8
R/W
-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSSL<15:0>: A/D Input Pin Scan Selection bits
1 = Corresponding analog channel is selected for input scan
0 = Analog channel is omitted from input scan