Datasheet

 2010 Microchip Technology Inc. DS39969B-page 317

PIC24FJ256DA210 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ACTLINE7 ACTLINE6 ACTLINE5 ACTLINE4 ACTLINE3 ACTLINE2 ACTLINE1 ACTLINE0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ACTPIX7 ACTPIX6 ACTPIX5 ACTPIX4 ACTPIX3 ACTPIX2 ACTPIX1 ACTPIX0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 ACTLINE<7:0>: Number of Lines Before the First Active (Displayed) Line bits

Typically, ACTLINEx = VENSTx (G1DBLCON<15:8>).

This register is added for versatility in the timing of the active lines.

For TFT mode, DPMODE bits (G1CON2<2:0>) = 001; the minimum value is 2.

For STN mode, DPMODE bits (G1CON2<2:0>) = 010,011,100; the minimum value is 0.

bit 7-0 ACTPIX<7:0>: Number of Pixels Before the First Active (Displayed) Pixel bits (in DISPCLKs)

Typically, ACTPIXx = HENSTx (G1DBLCON<7:0>).

This register is added for versatility in the timing of the active pixels. Note that the programmed value

is computed in DISPCLK cycles. This value is dependent on the DPGWDTH bit (G1CON2<15:14>).

Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)”

for details.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HSLEN7 HSLEN6 HSLEN5 HSLEN4 HSLEN3 HSLEN2 HSLEN1 HSLEN0

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HSST7 HSST6 HSST5 HSST4 HSST3 HSST2 HSST1 HSST0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 HSLEN<7:0>: HSYNC Pulse-Width Configuration bits (in DISPCLKs)

DPHSOE bit (G1CON3<0>) must be set for the HSYNC signal to toggle; minimum value is 1.

bit 7-0 HSST<7:0>: HSYNC Start Delay Configuration bits (in DISPCLKs)

This is the number of DISPCLK cycles from the start of horizontal blanking to the start of HSYNC active.