Datasheet

 2010 Microchip Technology Inc. DS39969B-page 315
PIC24FJ256DA210 FAMILY
REGISTER 22-15: G1DPADRL: DISPLAY BUFFER START ADDRESS REGISTER LOW
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPADR15 DPADR14 DPADR13 DPADR12 DPADR11 DPADR10 DPADR9 DPADR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPADR7 DPADR6 DPADR5 DPADR4 DPADR3 DPADR2 DPADR1 DPADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 DPADR<15:0>: Display Buffer Start Address Low bits
Display buffer start address must point to an even byte address in memory.
REGISTER 22-16: G1DPADRH: DISPLAY BUFFER START ADDRESS REGISTER HIGH
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPADR23 DPADR22 DPADR21 DPADR20 DPADR19 DPADR18 DPADR17 DPADR16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 DPADR<23:16>: Display Buffer Start Address High bits
Display buffer start address must point to an even byte address in memory.
REGISTER 22-17: G1DPW: DISPLAY BUFFER WIDTH REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — DPW10 DPW9 DPW8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DPW7 DPW6 DPW5 DPW4 DPW3 DPW2 DPW1 DPW0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 DPW<10:0>: Display Frame Width bits (in pixels)