Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 314  2010 Microchip Technology Inc.
REGISTER 22-12: G1W2ADRH: GPU WORK AREA 2 START ADDRESS REGISTER HIGH
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W2ADR23 W2ADR22 W2ADR21 W2ADR20 W2ADR19 W2ADR18 W2ADR17 W2ADR16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 W2ADR<23:16>: GPU Work Area 2 Start Address High bits
Work area address must point to an even byte address in memory.
REGISTER 22-13: G1PUW: GPU WORK AREA WIDTH REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PUW10 PUW9 PUW8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PUW7 PUW6 PUW5 PUW4 PUW3 PUW2 PUW1 PUW0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 PUW<10:0>: GPU Work Area Width bits (in pixels)
REGISTER 22-14: G1PUH: GPU WORK AREA HEIGHT REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PUH10 PUH9 PUH8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PUH7 PUH6 PUH5 PUH4 PUH3 PUH2 PUH1 PUH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-0 PUH<10:0>: GPU Work Area Height bits (in pixels)